Single Bit Slice - HDL Design - Lecture Slides, Slides of Verilog and VHDL

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Project Step 2 – A single bit slice

of the ALU

Structural Modeling 1

Project Step Overview

• Write the Entity and Architecture for the carry chain bit slice block of the multifunction ALU
• Use it and the generic unit from Project Step 1 to generate a single slice of the ALU

Signals needed

• The single slice interface
  • Data – A, B
  • P block control – P(0 to 3)
  • K block control – K(0 to 3)
  • Carry In
  • Carry Out
  • R block control – R(0 to 3)
  • Results output – F
• Internal Signals for P and K, Pint and Kint

Plus component instantiations

• To instantiate a component that has been compiled into the library - First declare it in the declarative region of the architecture - This is easiest done by simply copying the Entity interface of the unit and changing ENTITY to COMPONENT, delete the IS, and change the END unit_name to END COMPONENT - Also, do a configuration also in this region

The instantiation

• Once declared and configured the unit can be use between the BEGIN and END of the ARCHITECTURE ( instantiated )
• Provide a label for the instantiation
• Use named signals to wire to the inputs and outputs.

Turn in requirements

• Turn in: (Carmen drop box)
  • A copy of your code
    • Your code will be very similar to every other students but it won’t be exact.
  • A copy of the complete waveform and a copy zoomed into 0 to 650ns
  • A copy of the listing file after you have “collapsed deltas” and set the radix to hex