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ECE2030A Fall 2008
Introduction to Computer Engineering
Exam
50 min in-class exam.
Close books, close notes.
NO calculator.
This exam is given under the Georgia Tech Honor Code System. You must
observe and sign the Honor Pledge: “I have neither given nor received aid on
this exam.” Your print name and signature below signifies your compliance
with this honor code.
Name (Print): __________ SOLUTION ____________________________
Signature: _________________________________________________
1. _____________ (30 pts)
2. _____________ (30 pts)
3. _____________ (40 pts)
Total (100 pts) ____________
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A^ Y
B (^) X
O3 O2 O1 O
CLR 4 bit Ripple Counter (^) CLK
- (30%) General Questions. (Circle one of the answers) 1.1. How many output bits will be generated when performing 5-bit by 5-bit integer multiplication? (a) 5 bits (b) 10 bits ANSWER (c) 25 bits (d) 32 bits
1.2. Given the latch shown below, which of the following could cause an unstable state? (a) A = B = 0 ANSWER (X=Y=1) (b) A = 1, B = 0 (c) A = 0, B = 1 (d) A = B = 1
1.3. Which of the following memory contains the least number of transistors? (a) One bit DRAM ANSWER (b) One bit RS Latch (2 nd^ most) (c) One bit Register (most) (d) One bit SRAM (2 nd^ least)
1.4. What is the capacity of 2 k^ x N where k= 21, N=32? (a) 8 M Bytes ANSWER (2 21 x 2^5 = 2^26 = 64 M Bits = 8 M Bytes) (b) 64 M Bytes (c) 2 M Bytes (d) 32 M bits
1.5. Which type of the following memory requires periodic refreshing to not lose data? (a) D Flip-Flop (b) DRAM ANSWER (has a capacitor that needs to be refreshed) (c) SRAM (d) On-chip L1 Cache
1.6. Given the Mod-N counter shown below, what is N? (a) 6 (b) 7 ANSWER (c) 8 (d) 9
O3:O1 = 0110, therefore resets after 6. Counts from 0 to 6, therefore is a modulo-7 counter.
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2.2. (10%) Given the following input waveforms CLK and X, please draw the corresponding timing diagram (or waveform) of Y and Z for each of the following circuits. Assume the initial states of all latches or flip-flops are unknown.
D Q
C
D Flip-
Flop
D Q
C
D Flip-
Flop
X
CLK
Z
CLK
X
Y
Y
Z
Q
Q
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2.3. (10%) Given the following input waveforms CLK and X, please draw the corresponding timing diagram (or waveform) of Y and Z for the following circuits using Toggle Flip Flops. Assume the initial states of all latches or flip-flops are Zero.
TE Q
C
Toggle
Flip-Flop
TE Q
C
X
CLK
Z
CLK
X
Y
Y
Z
Toggle
Flip-Flop
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3.2. (15%) Derive the State Table and simplify the equations with Karnaugh maps.
Present State Input (X) Next State Output P1 P0 U'/D N1 N0 C1 C 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1
C1 = P1. C0 = P0.
Alternate:
Present State Input (X) Next State Output P1 P0 U'/D N1 N0 C1 C 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0
C1 = N1. C0 = N0.
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The Next State logic for either method is the same.
For N1: P0 X (^00 01 11 ) P 0 0 0 0 1 1 1 0 1 1
(P0 P1) X P1 P
N1 P0 X P1 X P1P
For N0: P0 X (^00 01 11 ) P 0 1 0 0 0 1 1 1 0 1
(P0 P1)X P1P
N0 P0X P1X P1P
3.3. (15%) Draw the sequential logic of this counter of your design. You do not need to draw the internals of the D Flip-Flop, simply draw each D Flip-Flop as a block.
The diagram below shows the answer for when C1 = N1, and C0 = N0.
The diagram for the other solution is the same, except C1 is pulled from P1, and C0 from P0.
D F/F
D
C
Q
Q
D F/F
D
C
Q
Q
U/D
CLK C C
N
N1 P
P
