1 Square-memory implementations of large memories often support fast page-modes that allow a burst of consecutive
memory reads from within the same row of the square memory.
a) How does this benefit performance on a cache miss?
b) An additional improvement allows the processor to specify a different ordering of the consecutive memory reads.
For example, a processor might specify a burst of size 4 reads with offsets of 2-3-0-1 from the specified memory
address. How does this benefit performance on a cache miss?
2 a) For the 8-bit data 01001011
2
develop the Hamming codeword for one-bit error detection and correction:
121+241+42+41+2+481+82+81+2+84+8
11010010
C
1
C
2
D
0
C
4
D
1
D
2
D
3
C
8
D
4
D
5
D
6
D
7
123456789101112
Check bit C
1
looks at bit positions 3, 5, 7, 9, and 11
Check bit C
2
looks at bit positions 3, 6, 7, 10, and 11
Check bit C
4
looks at bit positions 5, 6, 7, and 12
Check bit C
8
looks at bit positions 9, 10, 11, and 12
b) If bit D
5
gets flipped (an error), then how would we be able to detect an error?
c) If bit D
5
gets flipped (an error), then how would we be able to know which bit to correct?
d) For the 8-bit data 11001001
2
develop the Hamming codeword for one-bit error detection and correction:
121+241+42+41+2+481+82+81+2+84+8
11010010
C
1
C
2
D
0
C
4
D
1
D
2
D
3
C
8
D
4
D
5
D
6
D
7
123456789101112
Name:___________________
Lecture 17 - 1
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