SRAM Organization-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

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Dynamic Random Access Memory (DRAM)

– Each cell stores bit with a capacitor and

transistor.

– Value must be refreshed every 10-100 ms.

– Sensitive to disturbances.

– Slower and cheaper than SRAM.

Basic DRAM Cell

Write:

• Drive bit line and Select row

Read:

• Pre-charge bit line to Vdd and Select row
• Cell and bit line share charges

Here, very small voltage changes occurs on the bit line therefore Sense amplifier is used to detect changes

• Apply Write to restore the value

Refresh

– Just do a dummy read to every

cell.

row select

bit

DRAM Organization 16 words x 8bit

16 super cells (words) of size 8 bits

internal row buffer

cols

rows

16 x 8 DRAM chip

addr

data

supercell (2,1)

2 bits /

8 bits /

memory controller (to CPU)

Reading DRAM Supercell (2,1)

Step 2(a): Column access strobe (CAS) selects column 1.

Step 2(b): Supercell (2,1) copied from buffer to data lines,

and eventually back to the CPU.

cols

rows

internal row buffer

16 x 8 DRAM chip

CAS = 1

addr

data

2 /

8 /

memory controller

supercell (2,1)

supercell (2,1)

To CPU

64 MB DRAM Memory Module

[8x8MB DRAM Chips]

: supercell (i,j)

addr (row = i, col = j)

Memory controller

DRAM 7

DRAM 0

(^63 5655484740393231 )

64-bit double word at main memory address A

bits 0-

bits 8-

bits 16-

bits 24-

bits 32-

bits 40-

bits 48-

bits 56-

64-bit doubleword

Page Mode DRAM: Motivation

Regular DRAM Organization:

• N rows x N column x M-bit
• Read & Write M-bit at a time
• Each M-bit access requires a RAS / CAS cycle

Fast Page Mode DRAM

• N x M “register” to save a row

A Row Address Junk

CAS_L

RAS_L

Col Address Row Address Col Address Junk

1st M-bit Access 2nd M-bit Access

N rows

N cols

DRAM

M bits

Row Address

Column Address

M-bit Output

Fast Page Mode DRAM .. Cont’d

- one RAS and 3 CAS: [RAS, CAS, CAS,

CAS, CAS]

- instead of with 4 RAS and 4 CAS:

[(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]