Sequential Logic Design: State Encoding, Pipelined Outputs, and Asynchronous Inputs, Slides of Digital Logic Design and Programming

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Sequential Logic Design

Lecture

• Agenda
  1. State Encoding
  2. Pipelined Outputs
  3. Asynchronous Inputs
• Announcements
  1. n/a

State Encoding

• State Variable Encoding
  • we can decide how we encode our state variables- there are advantages/disadvantages to different techniques
• Binary Encoding
  • straight encoding of states S0 = “00”S1 = “01” S2 = “10”S3 = “11”
  • for n states, there are log(n)/log(2) flip-flops needed
  • this gives the Least # of Flip-Flops
  • Good for “Area” constrained designs
  • Drawbacks: - multiple bits switch at the same time = Increased Noise & Power- the Next State Logic “F” is multi-level = Increased Power and Reduced Speed

State Encoding

• One-Hot Encoding
  • encoding one flip-flop for each state S0 = “0001” S1 = “0010” S2 = “0100” S3 = “1000”
  • for n states, there are n flip-flops needed
  • the combination logic for F is one level (i.e., a Decoder)
  • Good for Speed
  • Especially good for FPGA due to “Programmable Logic Block”
  • Drawbacks: - takes more area

State Encoding

• State Encoding Trade-Offs
  • We typically trade off Speed, Area, and Power

speed

area power

One-Hot

Binary Gray

Pipelined Outputs

• Pipelined Outputs
  • This gives a smaller Data Uncertainty window on the output
  • The only consideration is that the output is not present until one clock cycle later

Pipelined Outputs

• Pipelined Outputs
  • we use a 4 th^ process for this stage of the State Machine

PIPELINED_OUTPUTS : process (CLK) begin if (CLK’event and CLK='1') then end if;Out <= Next_Out; end process;

Asynchronous Inputs

• Asynchronous Inputs
  • We use D-Flip-Flops to take in the input
  • with one D-Flip-Flop, the input can still occur within the Setup/Hold window
  • the output of the first DFF may be metastable for a moment of time (trecovery)
  • a second DFF is used to latch in the metastable input after it has had time to settle
  • the output of the second flip-flop is now stable and synchronized as long as: Tclk > t recovery + t comb + t setup
  • where t comb is the delay of any combinational logic in the input path