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Information on designing digital logic circuits, focusing on state transition and clock skew. It includes equations for next state functions, state tables, and state diagrams. The document also discusses the longest and shortest paths, clock skew, and redesigning the circuit to improve performance.
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Step1: get next state function
0 (t+1) = X Q 0 (t)โ
1 (t+1) = Q 0 (t)+Q 1 (t)โ Step2: get state tableStep3: get state diagram CLK X Q Q 0 Q 1 10 10 1 11 01 00 1 10 10 10 1 01 11 10 0 00 NS (X = 1) NS (X = 0) Q Q 1 Q 0 00 0/ 11 10 01 1/ 0/ 1/ -/ -/ Docsity.com
Requirements:
c
pcq
pd
setup
ccq
cd
hold CLK CLK Longest path?
c
pcq
pd
setup T c
70 + 3*100 + 60 = 430 ps Max Frequency = 1/T c = 2.33 GHz Docsity.com
With clock skew:
c
pcq
pd
setup
skew
ccq
cd
hold
skew CLK CLK Shortest Path?
ccq
cd
hold
skew 50 + 55
skew T skew
85 ps Docsity.com
With clock skew:
c
pcq
pd
setup
skew
ccq
cd
hold
skew CLK CLK Redesign the circuit? Idea: increase shortest path, reduce longest path!
c
pcq
pd
setup
skew T c
skew
ccq
cd
hold
skew T skew
140 ps CLK CLK Docsity.com
00011011 A,B 0 Y C 0 000001010011 A,B,C 100101110110 Y 1 0 0 0 0 0 0 1 Docsity.com
Use C to select AโBโ and AB AโBโ = (A+B)โ Y 0 1 C A B Docsity.com
