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Static and Dynamic Relocation
This shows the basic hardware instruction cycle for a machine that uses static relocation and for one that uses dynamic relocation.
Static Relocation
Static relocation refers to address transformations being done before execution of a program begins. A typical hard- ware instruction cycle looks like this:
l o o p { w = M[ i n s t r c t r ] ; / ∗ f e t c h i n s t r u c t i o n ∗ / oc = Opcode (w ) ; a d r = A d d r e s s (w ) ; i n s t r c t r += 1 ; s w i t c h ( oc ) { c a s e 1 : r e g += M[ a d r ] ; / ∗ add ∗ / c a s e 2 : M[ a d r ] = r e g ; / ∗ s t o r e ∗ / c a s e 3 : i n s t r c t r = a d r ; / ∗ b r a n c h ∗ /
... } }
Dynamic Relocation
Dynamic relocation refers to address transformations being done during execution of a program. In what follows, the function NL map (for N ame Location map) maps the relocatable (virtual) address va given in the program into the real (physical) storage address pa:
pa = NL map ( va )
So, a typical hardware instruction cycle looks like this: l o o p { w = M[ NL map ( i n s t r c t r ) ] ; / ∗ f e t c h i n s t r u c t i o n ∗ / oc = Opcode (w ) ; a d r = A d d r e s s (w ) ; i n s t r c t r += 1 ; s w i t c h ( oc ) { c a s e 1 : r e g += M[ NL map ( a d r ) ] ; / ∗ add ∗ / c a s e 2 : M[ NL map ( a d r ) ] = r e g ; / ∗ s t o r e ∗ / c a s e 3 : i n s t r c t r = NL map ( a d r ) ; / ∗ b r a n c h ∗ /
... } }
Paging and Address Translation
This shows the function used to map a logical address to a physical address for some paging schemes. Throughout this handout, an address in virtual memory is a pair (logical page, offset) where logical page is the page number within the logical address space and offset the offset into that page. Also, page size is the size of the page (which is a multiple of 2). We will assume the entire program is in memory, so no error handling is given; were this assumption false, the situation where the requested address were not in memory would need to be handled (by generating a page fault and loading the necessary page).
Paging Address Translation by Direct Mapping
This method stores the page table in main memory and the address of this table in the process control block, in a register called the page table base register. Let the page table base register be called pt base register, and let memory represent the main store of the computer. Then:
p h y s i c a l a d d r e s s NL map ( ( l o g i c a l p a g e , o f f s e t ) ) { r e t u r n ( memory [ p t b a s e r e g i s t e r + l o g i c a l p a g e ] ∗ p a g e s i z e + o f f s e t ) ; }
In pictures, here is what is going on:
Paging Address Translation by Associative Mapping
In this algorithm, assoc page table represents an associative memory. This function can check a type of mem- ory called “associative memory” (or “lookaside memory” or “translation lookaside buffer”) that stores both a frame number and a page number. The search is done in parallel, and is much faster than a linear (or binary) search. The function returns the frame number associated with its argument:
p h y s i c a l a d d r e s s NL map ( ( l o g i c a l p a g e , o f f s e t ) ) { r e t u r n ( a s s o c p a g e t a b l e ( l o g i c a l p a g e ) ∗ p a g e s i z e + o f f s e t ) ; }
Paging Address Translation with Combined Associative and Direct Mapping
This combines the above two methods. The array page table is a small associative store that can hold only a few page numbers; there is also a page table kept in memory. For this method, we shall assume that if there is no entry for logical page in the associative memory, assoc page table returns −1. Taking everything else as in the previous two sections:
Segmentation and Address Translation
This shows the function used to map a logical address to a physical address for some segmentation schemes. Throughout this handout, an address in virtual memory is a pair (segment, offset) where segment is the segment number within the logical address space and offset the offset into that segment. We will assume the entire program is in memory, so no error handling is given; were this assumption false, the situation where the requested address were not in memory would need to be handled (by generating a segment fault and loading the necessary segment).
Segmentation
As with paging address translation with direct mapping, the segment table is stored in memory, and a pointer to its base in a register called the segment table base register. Let the segment table base register be called st base register, and let memory represent the main store of the computer. Then:
p h y s i c a l a d d r e s s NL map ( ( l o g i c a l p a g e , o f f s e t ) ) { r e t u r n ( memory [ s t b a s e r e g i s t e r + s e g m e n t ] + o f f s e t ) ; }
In pictures, here is what is going on:
Segmentation and Paging Combined
This shows the function used to map a logical address to a physical address for schemes combining paging and seg- mentation. Throughout this handout, page size is the size of the page (which is a multiple of 2), seg tbl base reg contains the address of the base of the segment table, and memory is the main store of the computer. We will assume the entire program is in memory, so no error handling is given; were this assumption false, the situation where the requested address were not in memory would need to be handled (by generating a fault and loading the appropriate data structure).
Segmented Paging
In this algorithm, the page tables are segmented. The virtual address is represented as a pair (logical page, offset), but the logical page consists of a pair (seg number, seg offset) indicating which segment number seg number of the page table the frame number frame no is stored in, and the offset seg offset from the base of that segment table. As usual, an associative memory is first checked; this will be represented by the function assoc page table, which returns the frame number if that is in the table, and −1 if not:
p h y s i c a l a d d r e s s NL map ( ( l o g i c a l p a g e , o f f s e t ) ) { i n t f r a m e n o : i n t e g e r ; ( ∗ number o f f r a m e ∗ ) i n t p g t b l b a s e : i n t e g e r ; ( ∗ a d d r. o f pa ge t a b l e s e g m e n t ∗ )
f r a m e n o = a s s o c p a g e t a b l e ( l o g i c a l p a g e ) ; i f ( f r a m e n o == −1){ p g t b l b a s e = memory [ s e g t b l b a s e r e g + s e g n u m b e r ] ; f r a m e n o = memory [ p g t b l b a s e + s e g o f f s e t ] ; } r e t u r n ( f r a m e n o ∗ p a g e s i z e + o f f s e t ) ; }
Paged Segmentation
In this algorithm, the segments are paged. The virtual address is represented as a pair (seg number, offset), but the offset consists of a pair (page number, page offset), indicating which page number page number of the segment seg number the frame number frame no is stored in, and the offset page offset from the base of that page. As usual, an associative memory is first checked; this will be represented by the function assoc page table, which returns the frame number if that is in the table, and −1 if not. Note it takes the segment number as an argument as well:
p h y s i c a l a d d r e s s NL map ( ( s e g n u m b e r , o f f s e t ) ) { i n t f r a m e n o : i n t e g e r ; ( ∗ number o f f r a m e ∗ ) i n t p g t b l b a s e : i n t e g e r ; ( ∗ a d d r. o f pa ge t a b l e s e g m e n t ∗ )
f r a m e n o = a s s o c p a g e t a b l e ( s e g n u m b e r , p a g e n u m b e r ) ; i f ( f r a m e n o == −1){ p g t b l b a s e = memory [ s e g t b l b a s e r e g + s e g n u m b e r ] ; f r a m e n o = memory [ p g t b l b a s e + p a g e n u m b e r ] ; } r e t u r n ( f r a m e n o ∗ p a g e s i z e + p a g e o f f s e t ) ; }
In pictures, here is what is going on:
Page Replacement Algorithms
This handout shows how the various page replacement algorithms work. We shall call the pages of the program a, b, c, ... to distinguish them from the time (1, 2, 3, ...).
Fixed Number of Frames
We shall demonstrate these algorithms by running them on the reference string ω = cadbebabcd and assume that, initialy, pages a, b, c, and doccupy frames 0, 1, 2, and 3 respectively. When appropriate, the little arrow → indicates the location of the “pointer” that indicates where the search for the next victim will begin.
First In/First Out (FIFO)
This policy replaces pages in the order of arrival in memory.
time 0 1 2 3 4 5 6 7 8 9 10 ω c a d b e b a b c d frame 0 →a →a →a →a →a e e e e →e d frame 1 b b b b b →b →b a a a →a frame 2 c c c c c c c →c b b b frame 3 d d d d d d d d →d c c page fault 1 2 3 4 5 page(s) loaded e a b c d page(s) removed a b c d e
Optimal (OPT, MIN)
This policy selects for replacement the page that will not be referenced for the longest time in the future.
time 0 1 2 3 4 5 6 7 8 9 10 ω c a d b e b a b c d frame 0 a a a a a a a a a a d frame 1 b b b b b b b b b b b frame 2 c c c c c c c c c c c frame 3 d d d d d e e e e e e page fault 1 2 page(s) loaded e d page(s) removed d a
Least Recently Used (LRU)
This policy selects for replacement the page that has not been used for the longest period of time.
time 0 1 2 3 4 5 6 7 8 9 10 ω c a d b e b a b c d frame 0 a a a a a a a a a a a frame 1 b b b b b b b b b b b frame 2 c c c c c e e e e e d frame 3 d d d d d d d d d c c page fault 1 2 3 page(s) loaded e c d page(s) removed c d e stack (top) c a d b e b a b c d
- c a d b e b a b c
- – c a d d e e a b stack (bottom) – – – c a a d d e a
Not-Recently-Used or Not Used Recently (NRU, NUR)
This policy selects for replacement a random page from the following classes (in the order given): not used or modified, not used but modified, used and not modified, used and modified. In the following, assume references at times 2, 4, and 7 are writes (represented by the bold page references). The two numbers written after each page are the use and modified bits, respectively.
time 0 1 2 3 4 5 6 7 8 9 10 ω c a d b e b a b c d frame 0 a/00 a/00 a/11 a/11 a/11 a/01 a/01 a/11 a/11 a/01 a/ frame 1 b/00 b/00 b/00 b/00 b/11 b/01 b/11 b/11 b/11 b/01 b/ frame 2 c/00 c/10 c/10 c/10 c/10 e/10 e/10 e/10 e/10 e/00 d/ frame 3 d/00 d/00 d/00 d/10 d/10 d/00 d/00 d/00 d/00 c/10 c/ page fault 1 2 3 page(s) loaded e c d page(s) removed c d e
Clock
This policy is similar to LRU and FIFO. Whenever a page is referenced, the use bit is set. When a page must be replaced, the algorithm begins with the page frame pointed to. If the frame’s use bit is set, it is cleared and the pointer advanced. If not, the page in that frame is replaced. Here the number after the page is the use bit; we’ll assume all pages have been referenced initially.
time 0 1 2 3 4 5 6 7 8 9 10 ω c a d b e b a b c d frame 0 a/0 →a/0 →a/1 →a/1 →a/1 e/1 e/1 e/1 e/1 →e/1 d/ frame 1 b/0 b/0 b/0 b/0 b/1 →b/0 →b/1 b/0 b/1 b/1 b/ frame 2 c/0 c/1 c/1 c/1 c/1 c/0 c/0 a/1 a/1 a/1 a/ frame 3 d/0 d/0 d/0 d/1 d/1 d/0 d/0 →d/0 →d/0 c/1 c/ page fault 1 2 3 4 page(s) loaded e a c d page(s) removed a c d e
Second-chance Cyclic
This policy merges the clock algorithm and the NRU algorithm. Each page frame has a use and a modified bit. Whenever a page is referenced, the use bit is set; whenever modified, the modify bit is set. When a page must be replaced, the algorithm begins with the page frame pointed to. If the frame’s use bit and modify bit are set, the use bit is cleared and the pointer advanced; if the use bit is set but the modify bit is not, the use bit is cleared and the pointer advanced; if the use bit is clear but the modify bit is set, the modify bit is cleared (and the algorithm notes that the page must be copied out before being replaced; here, the page is emboldened) and the pointer is advanced; if both the use and modify bits are clear, the page in that frame is replaced. In the following, assume references at times 2, 4, and 7 are writes (represented by the bold page references). The two numbers written after each page are the use and modified bits, respectively. Initially, all pages have been used but none are modified.
time 0 1 2 3 4 5 6 7 8 9 10 ω c a d b e b a b c d frame 0 a/00 →a/00 →a/11 →a/11 →a/11 a/00 a/00 a/11 a/11 →a/11 a/ frame 1 b/00 b/00 b/00 b/00 b/11 b/00 b/10 b/10 b/10 b/10 d/ frame 2 c/00 c/10 c/10 c/10 c/10 e/10 e/10 e/10 e/10 e/10 →e/ frame 3 d/00 d/00 d/00 d/10 d/10 →d/00 →d/00 →d/00 →d/00 c/10 c/ fault 1 2 3 loaded e c d removed c d e
