Study Guide for Microprocessor Systems | CPEG 222, Assignments of Microprocessors

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HCS

Microcontrollers

freescale.com

MC9S08GB

MC9S08GB

MC9S08GT

MC9S08GT

MC9S08GT

Data Sheet

MC9S08GB60/D

Rev. 2. 12/

MC9S08GB/GT Data Sheet, Rev. 2.

Revision History

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The following revision history table summarizes changes contained in this document.

This product incorporates SuperFlash®^ technology licensed from SST.

Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2004. All rights reserved.

Revision Number

Revision Date Description of Changes 1.0 4/25/2003 Initial release 1.1 Electricals change, appendix A only 1.2 Electricals change, appendix A only 1.3 10/2/2003 Added module version table; clarifications 1.4 10/29/2003 Fixed typos and made corrections and clarifications 1.5 11/12/2003 Added 1-MHz IDD values to Electricals, appendix A

2 2/10/

Changed format of register names to enable reuse of code (from SCIBD to SCI1BD, even when only one instance of a module on a chip) Added new device: MC9S08GT16 to book. Added new 48-pin QFN package to book. BKGDPE description in Section 5 — changed PTD0 to PTG0. Changed typo in CPU section that listed MOV instruction as being 6 cycles instead of 5 (Table 8-2).

2.2 9/2/

Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5; updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1; updated ICG electricals Table A-9 and added a figure

2.3 12/01/

Minor changes to Table 7-4, Table 7-5, Table A-9; Clarifications in Section 11.10.6, “SCI x Control Register 3 (SCIxC3)”, Section 11.7, “Interrupts and Status Flags”, Section 11.8.1, “8- and 9-Bit Data Modes”, PTG availability in 48-pin package (see Table 2-2)

List of Chapters

Introduction

Contents

Appendix A

Appendix B

• Covers: MC9S08GB
  • MC9S08GB
  • MC9S08GT
  • MC9S08GT
  • MC9S08GT
    • MC9S08GB
      • Rev. 2.
        • 12/
  • MC9S08GB/GT Data Sheet, Rev. 2.
• Chapter 1 Introduction..............................................................................
• Chapter 2 Pins and Connections
• Chapter 3 Modes of Operation
• Chapter 4 Memory
• Chapter 5 Resets, Interrupts, and System Configuration
• Chapter 6 Parallel Input/Output
• Chapter 7 Internal Clock Generator (ICG) Module
• Chapter 8 Central Processor Unit (CPU)...............................................
• Chapter 9 Keyboard Interrupt (KBI) Module
• Chapter 10 Timer/PWM (TPM) Module.....................................................
• Chapter 11 Serial Communications Interface (SCI) Module..................
• Chapter 12 Serial Peripheral Interface (SPI) Module..............................
• Chapter 13 Inter-Integrated Circuit (IIC) Module
• Chapter 14 Analog-to-Digital Converter (ATD) Module
• Chapter 15 Development Support
• Appendix A Electrical Characteristics......................................................
• Appendix B Ordering Information and Mechanical Drawings................ - MC9S08GB/GT Data Sheet, Rev. 2. - Chapter
• 1.1 Overview .........................................................................................................................................
• 1.2 Features ...........................................................................................................................................
  • 1.2.1 Standard Features of the HCS08 Family .........................................................................
  • 1.2.2 Features of MC9S08GB/GT Series of MCUs .................................................................
  • 1.2.3 Devices in the MC9S08GB/GT Series ............................................................................
• 1.3 MCU Block Diagrams .....................................................................................................................
• 1.4 System Clock Distribution .............................................................................................................. - Chapter
• 2.1 Introduction ..................................................................................................................................... Pins and Connections
• 2.2 Device Pin Assignment ...................................................................................................................
• 2.3 Recommended System Connections ...............................................................................................
  • 2.3.1 Power ...............................................................................................................................
  • 2.3.2 Oscillator ..........................................................................................................................
  • 2.3.3 Reset ................................................................................................................................
  • 2.3.4 Background / Mode Select (PTG0/BKGD/MS) ..............................................................
  • 2.3.5 General-Purpose I/O and Peripheral Ports .......................................................................
  • 2.3.6 Signal Properties Summary ............................................................................................. - Chapter
• 3.1 Introduction ..................................................................................................................................... Modes of Operation
• 3.2 Features ...........................................................................................................................................
• 3.3 Run Mode ........................................................................................................................................
• 3.4 Active Background Mode ................................................................................................................
• 3.5 Wait Mode .......................................................................................................................................
• 3.6 Stop Modes ......................................................................................................................................
  • 3.6.1 Stop1 Mode ......................................................................................................................
  • 3.6.2 Stop2 Mode ......................................................................................................................
  • 3.6.3 Stop3 Mode ......................................................................................................................
  • 3.6.4 Active BDM Enabled in Stop Mode ................................................................................
  • 3.6.5 LVD Enabled in Stop Mode .............................................................................................
  • 3.6.6 On-Chip Peripheral Modules in Stop Modes ................................................................... - MC9S08GB/GT Data Sheet, Rev. 2. - Chapter Section Number Title Page
• 4.1 MC9S08GB/GT Memory Map ....................................................................................................... Memory
  • 4.1.1 Reset and Interrupt Vector Assignments ..........................................................................
• 4.2 Register Addresses and Bit Assignments ........................................................................................
• 4.3 RAM ................................................................................................................................................
• 4.4 FLASH ............................................................................................................................................
  • 4.4.1 Features ............................................................................................................................
  • 4.4.2 Program and Erase Times ................................................................................................
  • 4.4.3 Program and Erase Command Execution ........................................................................
  • 4.4.4 Burst Program Execution .................................................................................................
  • 4.4.5 Access Errors ...................................................................................................................
  • 4.4.6 FLASH Block Protection .................................................................................................
  • 4.4.7 Vector Redirection ...........................................................................................................
• 4.5 Security ............................................................................................................................................
• 4.6 FLASH Registers and Control Bits .................................................................................................
  • 4.6.1 FLASH Clock Divider Register (FCDIV) .......................................................................
  • 4.6.2 FLASH Options Register (FOPT and NVOPT) ..............................................................
  • 4.6.3 FLASH Configuration Register (FCNFG) .......................................................................
  • 4.6.4 FLASH Protection Register (FPROT and NVPROT) ......................................................
  • 4.6.5 FLASH Status Register (FSTAT) .....................................................................................
  • 4.6.6 FLASH Command Register (FCMD) .............................................................................. - Chapter
• 5.1 Introduction ..................................................................................................................................... Resets, Interrupts, and System Configuration
• 5.2 Features ...........................................................................................................................................
• 5.3 MCU Reset ......................................................................................................................................
• 5.4 Computer Operating Properly (COP) Watchdog .............................................................................
• 5.5 Interrupts .........................................................................................................................................
  • 5.5.1 Interrupt Stack Frame ......................................................................................................
  • 5.5.2 External Interrupt Request (IRQ) Pin ..............................................................................
    • 5.5.2.1 Pin Configuration Options ..............................................................................
    • 5.5.2.2 Edge and Level Sensitivity ..............................................................................
  • 5.5.3 Interrupt Vectors, Sources, and Local Masks ..................................................................
• 5.6 Low-Voltage Detect (LVD) System ................................................................................................
  • 5.6.1 Power-On Reset Operation ..............................................................................................
  • 5.6.2 LVD Reset Operation .......................................................................................................
  • 5.6.3 LVD Interrupt Operation .................................................................................................
  • 5.6.4 Low-Voltage Warning (LVW) ..........................................................................................
• 5.7 Real-Time Interrupt (RTI) ............................................................................................................... - MC9S08GB/GT Data Sheet, Rev. 2.
• 5.8 Reset, Interrupt, and System Control Registers and Control Bits ................................................... Section Number Title Page
  • 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................
  • 5.8.2 System Reset Status Register (SRS) ................................................................................
  • 5.8.3 System Background Debug Force Reset Register (SBDFR) ...........................................
  • 5.8.4 System Options Register (SOPT) ....................................................................................
  • 5.8.5 System Device Identification Register (SDIDH, SDIDL) ...............................................
  • 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) ...............................
  • 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ..........................
  • 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) .......................... - Chapter
• 6.1 Introduction ..................................................................................................................................... Parallel Input/Output
• 6.2 Features ...........................................................................................................................................
• 6.3 Pin Descriptions ..............................................................................................................................
  • 6.3.1 Port A and Keyboard Interrupts .......................................................................................
  • 6.3.2 Port B and Analog to Digital Converter Inputs ...............................................................
  • 6.3.3 Port C and SCI2, IIC, and High-Current Drivers ............................................................
  • 6.3.4 Port D, TPM1 and TPM2 .................................................................................................
  • 6.3.5 Port E, SCI1, and SPI ......................................................................................................
  • 6.3.6 Port F and High-Current Drivers .....................................................................................
  • 6.3.7 Port G, BKGD/MS, and Oscillator ..................................................................................
• 6.4 Parallel I/O Controls ........................................................................................................................
  • 6.4.1 Data Direction Control ....................................................................................................
  • 6.4.2 Internal Pullup Control ....................................................................................................
  • 6.4.3 Slew Rate Control ............................................................................................................
• 6.5 Stop Modes ......................................................................................................................................
• 6.6 Parallel I/O Registers and Control Bits ...........................................................................................
  • 6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) ................................................
  • 6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) ...............................................
  • 6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) ...............................................
  • 6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ..............................................
  • 6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ................................................
  • 6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) ..................................................
  • 6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) .............................................. - MC9S08GB/GT Data Sheet, Rev. 2. - Chapter Section Number Title Page
• 7.1 Introduction ..................................................................................................................................... Internal Clock Generator (ICG) Module
  • 7.1.1 Features ..........................................................................................................................
  • 7.1.2 Modes of Operation .......................................................................................................
• 7.2 External Signal Description ..........................................................................................................
  • 7.2.1 Overview ........................................................................................................................
  • 7.2.2 Detailed Signal Descriptions .........................................................................................
    • 7.2.2.1 EXTAL— External Reference Clock / Oscillator Input ...............................
    • 7.2.2.2 XTAL— Oscillator Output ...........................................................................
  • 7.2.3 External Clock Connections ..........................................................................................
  • 7.2.4 External Crystal/Resonator Connections .......................................................................
• 7.3 Functional Description ..................................................................................................................
  • 7.3.1 Off Mode (Off) ..............................................................................................................
    • 7.3.1.1 BDM Active .................................................................................................
    • 7.3.1.2 OSCSTEN Bit Set .........................................................................................
    • 7.3.1.3 Stop/Off Mode Recovery ..............................................................................
  • 7.3.2 Self-Clocked Mode (SCM) ............................................................................................
  • 7.3.3 FLL Engaged, Internal Clock (FEI) Mode ....................................................................
    • 7.3.3.1 FLL Engaged Internal Unlocked ..................................................................
    • 7.3.3.2 FLL Engaged Internal Locked ......................................................................
  • 7.3.4 FLL Bypassed, External Clock (FBE) Mode ................................................................
  • 7.3.5 FLL Engaged, External Clock (FEE) Mode ..................................................................
    • 7.3.5.1 FLL Engaged External Unlocked .................................................................
    • 7.3.5.2 FLL Engaged External Locked .....................................................................
  • 7.3.6 FLL Lock and Loss-of-Lock Detection .........................................................................
  • 7.3.7 FLL Loss-of-Clock Detection ........................................................................................
  • 7.3.8 Clock Mode Requirements ............................................................................................
  • 7.3.9 Fixed Frequency Clock ..................................................................................................
• 7.4 Initialization/Application Information ..........................................................................................
  • 7.4.1 Introduction ....................................................................................................................
  • 7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz .........................
  • 7.4.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................
  • 7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency .....................
  • 7.4.5 Example #4: Internal Clock Generator Trim .................................................................
• 7.5 ICG Registers and Control Bits .....................................................................................................
  • 7.5.1 ICG Control Register 1 (ICGC1) ......................................................................
  • 7.5.2 ICG Control Register 2 (ICGC2) ......................................................................
  • 7.5.3 ICG Status Register 1 (ICGS1) .................................................................................
  • 7.5.4 ICG Status Register 2 (ICGS2) ........................................................................
  • 7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL) .......................................................
  • 7.5.6 ICG Trim Register (ICGTRM) ........................................................................... - MC9S08GB/GT Data Sheet, Rev. 2. - Chapter Section Number Title Page
• 8.1 Introduction ................................................................................................................................... Central Processor Unit (CPU)
• 8.2 Features .........................................................................................................................................
• 8.3 Programmer’s Model and CPU Registers .....................................................................................
  • 8.3.1 Accumulator (A) ............................................................................................................
  • 8.3.2 Index Register (H:X) .....................................................................................................
  • 8.3.3 Stack Pointer (SP) ..........................................................................................................
  • 8.3.4 Program Counter (PC) ...................................................................................................
  • 8.3.5 Condition Code Register (CCR) ....................................................................................
• 8.4 Addressing Modes .........................................................................................................................
  • 8.4.1 Inherent Addressing Mode (INH) ..................................................................................
  • 8.4.2 Relative Addressing Mode (REL) .................................................................................
  • 8.4.3 Immediate Addressing Mode (IMM) .............................................................................
  • 8.4.4 Direct Addressing Mode (DIR) .....................................................................................
  • 8.4.5 Extended Addressing Mode (EXT) ...............................................................................
  • 8.4.6 Indexed Addressing Mode .............................................................................................
    • 8.4.6.1 Indexed, No Offset (IX) ................................................................................
    • 8.4.6.2 Indexed, No Offset with Post Increment (IX+) .............................................
    • 8.4.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................
    • 8.4.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................
    • 8.4.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................
    • 8.4.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................
    • 8.4.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................
• 8.5 Special Operations .........................................................................................................................
  • 8.5.1 Reset Sequence ..............................................................................................................
  • 8.5.2 Interrupt Sequence .........................................................................................................
  • 8.5.3 Wait Mode Operation .....................................................................................................
  • 8.5.4 Stop Mode Operation .....................................................................................................
  • 8.5.5 BGND Instruction ..........................................................................................................
• 8.6 HCS08 Instruction Set Summary .................................................................................................. - Chapter
• 9.1 Introduction ................................................................................................................................... Keyboard Interrupt (KBI) Module
  • 9.1.1 Port A and Keyboard Interrupt Pins ..............................................................................
• 9.2 Features .........................................................................................................................................
• 9.3 KBI Block Diagram ......................................................................................................................
• 9.4 Keyboard Interrupt (KBI) Module ................................................................................................
  • 9.4.1 Pin Enables ....................................................................................................................
  • 9.4.2 Edge and Level Sensitivity ............................................................................................
  • 9.4.3 KBI Interrupt Controls ...................................................................................................
• 9.5 KBI Registers and Control Bits .....................................................................................................
  • 9.5.1 KBI Status and Control Register (KBI1SC) ..................................................................
  • 9.5.2 KBI Pin Enable Register (KBI1PE) .............................................................................. - MC9S08GB/GT Data Sheet, Rev. 2. - Chapter Section Number Title Page
• 10.1 Introduction ................................................................................................................................... Timer/PWM (TPM) Module
• 10.2 Features .........................................................................................................................................
• 10.3 TPM Block Diagram .....................................................................................................................
• 10.4 Pin Descriptions ............................................................................................................................
  • 10.4.1 External TPM Clock Sources ........................................................................................
  • 10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................
• 10.5 Functional Description ..................................................................................................................
  • 10.5.1 Counter ..........................................................................................................................
  • 10.5.2 Channel Mode Selection ................................................................................................
    • 10.5.2.1 Input Capture Mode ......................................................................................
    • 10.5.2.2 Output Compare Mode .................................................................................
    • 10.5.2.3 Edge-Aligned PWM Mode ...........................................................................
  • 10.5.3 Center-Aligned PWM Mode ..........................................................................................
• 10.6 TPM Interrupts ..............................................................................................................................
  • 10.6.1 Clearing Timer Interrupt Flags ......................................................................................
  • 10.6.2 Timer Overflow Interrupt Description ...........................................................................
  • 10.6.3 Channel Event Interrupt Description .............................................................................
  • 10.6.4 PWM End-of-Duty-Cycle Events ..................................................................................
• 10.7 TPM Registers and Control Bits ...................................................................................................
  • 10.7.1 Timer x Status and Control Register (TPMxSC) ...........................................................
  • 10.7.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ..............................................
  • 10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ..............................
  • 10.7.4 Timer x Channel n Status and Control Register (TPMxCnSC) .....................................
  • 10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ..................................... - Chapter
• 11.1 Introduction ................................................................................................................................... Serial Communications Interface (SCI) Module
• 11.2 Features .........................................................................................................................................
• 11.3 SCI System Description ................................................................................................................
• 11.4 Baud Rate Generation ...................................................................................................................
• 11.5 Transmitter Functional Description ...............................................................................................
  • 11.5.1 Transmitter Block Diagram ...........................................................................................
  • 11.5.2 Send Break and Queued Idle .........................................................................................
• 11.6 Receiver Functional Description ...................................................................................................
  • 11.6.1 Receiver Block Diagram ................................................................................................
  • 11.6.2 Data Sampling Technique ..............................................................................................
  • 11.6.3 Receiver Wakeup Operation ..........................................................................................
    • 11.6.3.1 Idle-Line Wakeup ..........................................................................................
    • 11.6.3.2 Address-Mark Wakeup .................................................................................
• 11.7 Interrupts and Status Flags ............................................................................................................ - MC9S08GB/GT Data Sheet, Rev. 2.
• 11.8 Additional SCI Functions .............................................................................................................. Section Number Title Page
  • 11.8.1 8- and 9-Bit Data Modes ................................................................................................
• 11.9 Stop Mode Operation ....................................................................................................................
  • 11.9.1 Loop Mode .....................................................................................................................
  • 11.9.2 Single-Wire Operation ...................................................................................................
• 11.10 SCI Registers and Control Bits .....................................................................................................
  • 11.10.1 SCI x Baud Rate Registers (SCIxBDH, SCIxBDL) ......................................................
  • 11.10.2 SCI x Control Register 1 (SCIxC1) ...............................................................................
  • 11.10.3 SCI x Control Register 2 (SCIxC2) ...............................................................................
  • 11.10.4 SCI x Status Register 1 (SCIxS1) ..................................................................................
  • 11.10.5 SCI x Status Register 2 (SCIxS2) ..................................................................................
  • 11.10.6 SCI x Control Register 3 (SCIxC3) ...............................................................................
  • 11.10.7 SCI x Data Register (SCIxD) ........................................................................................ - Chapter
• 12.1 Features ......................................................................................................................................... Serial Peripheral Interface (SPI) Module
• 12.2 Block Diagrams .............................................................................................................................
  • 12.2.1 SPI System Block Diagram ...........................................................................................
  • 12.2.2 SPI Module Block Diagram ...........................................................................................
  • 12.2.3 SPI Baud Rate Generation .............................................................................................
• 12.3 Functional Description ..................................................................................................................
  • 12.3.1 SPI Clock Formats .........................................................................................................
  • 12.3.2 SPI Pin Controls ............................................................................................................
    • 12.3.2.1 SPSCK1 — SPI Serial Clock ........................................................................
    • 12.3.2.2 MOSI1 — Master Data Out, Slave Data In ..................................................
    • 12.3.2.3 MISO1 — Master Data In, Slave Data Out ..................................................
    • 12.3.2.4 SS1 — Slave Select .......................................................................................
  • 12.3.3 SPI Interrupts .................................................................................................................
  • 12.3.4 Mode Fault Detection ....................................................................................................
• 12.4 SPI Registers and Control Bits ......................................................................................................
  • 12.4.1 SPI Control Register 1 (SPI1C1) ...................................................................................
  • 12.4.2 SPI Control Register 2 (SPI1C2) ...................................................................................
  • 12.4.3 SPI Baud Rate Register (SPI1BR) .................................................................................
  • 12.4.4 SPI Status Register (SPI1S) ...........................................................................................
  • 12.4.5 SPI Data Register (SPI1D) ............................................................................................ - MC9S08GB/GT Data Sheet, Rev. 2. - Chapter Section Number Title Page
• 13.1 Introduction ................................................................................................................................... Inter-Integrated Circuit (IIC) Module
  • 13.1.1 Features ..........................................................................................................................
  • 13.1.2 Modes of Operation .......................................................................................................
  • 13.1.3 Block Diagram ...............................................................................................................
  • 13.1.4 Detailed Signal Descriptions .........................................................................................
    • 13.1.4.1 SCL1 — Serial Clock Line ...........................................................................
    • 13.1.4.2 SDA1 — Serial Data Line ............................................................................
• 13.2 Functional Description ..................................................................................................................
  • 13.2.1 IIC Protocol ...................................................................................................................
    • 13.2.1.1 START Signal ...............................................................................................
    • 13.2.1.2 Slave Address Transmission .........................................................................
    • 13.2.1.3 Data Transfer .................................................................................................
    • 13.2.1.4 STOP Signal ..................................................................................................
    • 13.2.1.5 Repeated START Signal ...............................................................................
    • 13.2.1.6 Arbitration Procedure ....................................................................................
    • 13.2.1.7 Clock Synchronization ..................................................................................
    • 13.2.1.8 Handshaking .................................................................................................
    • 13.2.1.9 Clock Stretching ............................................................................................
• 13.3 Resets ............................................................................................................................................
• 13.4 Interrupts .......................................................................................................................................
  • 13.4.1 Byte Transfer Interrupt ..................................................................................................
  • 13.4.2 Address Detect Interrupt ................................................................................................
  • 13.4.3 Arbitration Lost Interrupt ..............................................................................................
• 13.5 IIC Registers and Control Bits ......................................................................................................
  • 13.5.1 IIC Address Register (IIC1A) ........................................................................................
  • 13.5.2 IIC Frequency Divider Register (IIC1F) ........................................................................
  • 13.5.3 IIC Control Register (IIC1C) .........................................................................................
  • 13.5.4 IIC Status Register (IIC1S) ............................................................................................
  • 13.5.5 IIC Data I/O Register (IIC1D) ....................................................................................... - Chapter
• 14.1 Introduction ................................................................................................................................... Analog-to-Digital Converter (ATD) Module
  • 14.1.1 Features ..........................................................................................................................
  • 14.1.2 Modes of Operation .......................................................................................................
    • 14.1.2.1 Stop Mode .....................................................................................................
    • 14.1.2.2 Power Down Mode .......................................................................................
  • 14.1.3 Block Diagram ...............................................................................................................
• 14.2 Signal Description .........................................................................................................................
  • 14.2.1 Overview ........................................................................................................................
    • 14.2.1.1 Channel Input Pins — AD1P7–AD1P0 ........................................................
      • MC9S08GB/GT Data Sheet, Rev. 2.
    • 14.2.1.2 ATD Reference Pins — VREFH , V REFL ........................................................ Section Number Title Page
    • 14.2.1.3 ATD Supply Pins — V DDAD , VSSAD ...........................................................
• 14.3 Functional Description ..................................................................................................................
  • 14.3.1 Mode Control .................................................................................................................
  • 14.3.2 Sample and Hold ............................................................................................................
  • 14.3.3 Analog Input Multiplexer ..............................................................................................
  • 14.3.4 ATD Module Accuracy Definitions ...............................................................................
• 14.4 Resets ............................................................................................................................................
• 14.5 Interrupts .......................................................................................................................................
• 14.6 ATD Registers and Control Bits ....................................................................................................
  • 14.6.1 ATD Control (ATDC) ....................................................................................................
  • 14.6.2 ATD Status and Control (ATD1SC) ..............................................................................
  • 14.6.3 ATD Result Data (ATD1RH, ATD1RL) ........................................................................
  • 14.6.4 ATD Pin Enable (ATD1PE) ........................................................................................... - Chapter
• 15.1 Introduction ................................................................................................................................... Development Support
• 15.2 Features .........................................................................................................................................
• 15.3 Background Debug Controller (BDC) ..........................................................................................
  • 15.3.1 BKGD Pin Description ..................................................................................................
  • 15.3.2 Communication Details .................................................................................................
  • 15.3.3 BDC Commands ............................................................................................................
  • 15.3.4 BDC Hardware Breakpoint ............................................................................................
• 15.4 On-Chip Debug System (DBG) ....................................................................................................
  • 15.4.1 Comparators A and B ....................................................................................................
  • 15.4.2 Bus Capture Information and FIFO Operation ..............................................................
  • 15.4.3 Change-of-Flow Information .........................................................................................
  • 15.4.4 Tag vs. Force Breakpoints and Triggers ........................................................................
  • 15.4.5 Trigger Modes ................................................................................................................
  • 15.4.6 Hardware Breakpoints ...................................................................................................
• 15.5 Registers and Control Bits .............................................................................................................
  • 15.5.1 BDC Registers and Control Bits ....................................................................................
    • 15.5.1.1 BDC Status and Control Register (BDCSCR) ..............................................
    • 15.5.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................
  • 15.5.2 System Background Debug Force Reset Register (SBDFR) .........................................
  • 15.5.3 DBG Registers and Control Bits ....................................................................................
    • 15.5.3.1 Debug Comparator A High Register (DBGCAH) ........................................
    • 15.5.3.2 Debug Comparator A Low Register (DBGCAL) .........................................
    • 15.5.3.3 Debug Comparator B High Register (DBGCBH) .........................................
    • 15.5.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................
      • MC9S08GB/GT Data Sheet, Rev. 2.
    • 15.5.3.5 Debug FIFO High Register (DBGFH) .......................................................... Section Number Title Page
    • 15.5.3.6 Debug FIFO Low Register (DBGFL) ...........................................................
    • 15.5.3.7 Debug Control Register (DBGC) ..................................................................
    • 15.5.3.8 Debug Trigger Register (DBGT) ..................................................................
    • 15.5.3.9 Debug Status Register (DBGS) .....................................................................
• A.1 Introduction ................................................................................................................................... Electrical Characteristics
• A.2 Absolute Maximum Ratings ..........................................................................................................
• A.3 Thermal Characteristics .................................................................................................................
• A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................
• A.5 DC Characteristics .........................................................................................................................
• A.6 Supply Current Characteristics ......................................................................................................
• A.7 ATD Characteristics ......................................................................................................................
• A.8 Internal Clock Generation Module Characteristics .......................................................................
  • A.8.1 ICG Frequency Specifications ........................................................................................
• A.9 AC Characteristics .........................................................................................................................
  • A.9.1 Control Timing ...............................................................................................................
  • A.9.2 Timer/PWM (TPM) Module Timing ..............................................................................
  • A.9.3 SPI Timing ......................................................................................................................
• A.10 FLASH Specifications ...................................................................................................................
• B.1 Ordering Information .................................................................................................................... Ordering Information and Mechanical Drawings
• B.2 Mechanical Drawings ....................................................................................................................
• B.3 64-Pin LQFP Package Drawing ....................................................................................................
• B.4 48-Pin QFN Package Drawing ......................................................................................................
• B.5 44-Pin QFP Package Drawing .......................................................................................................
• B.6 42-Pin SDIP Package Drawing .....................................................................................................

MC9S08GB/GT Data Sheet, Rev. 2.

Chapter 1 Introduction

1.1 Overview

The MC9S08GB/GT are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types.

1.2 Features

Features have been organized to reflect:

• Standard features of the HCS08 Family
• Features of the MC9S08GB/GT MCU

1.2.1 Standard Features of the HCS08 Family

• 40-MHz HCS08 CPU (central processor unit)
• HC08 instruction set with added BGND instruction
• Background debugging system (see also Chapter 15, “Development Support”)
• Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
• Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints.
• Support for up to 32 interrupt/reset sources
• Power-saving modes: wait plus three stops
• System protection features: — Optional computer operating properly (COP) reset — Low-voltage detection with reset or interrupt — Illegal opcode detection with reset — Illegal address detection with reset (some devices don’t have illegal addresses)

1.2.2 Features of MC9S08GB/GT Series of MCUs

• On-chip in-circuit programmable FLASH memory with block protection and security options (see Table 1-1 for device specific information)
• On-chip random-access memory (RAM) (see Table 1-1 for device specific information)
• 8-channel, 10-bit analog-to-digital converter (ATD)
• Two serial communications interface modules (SCI)
• Serial peripheral interface module (SPI)

MCU Block Diagrams

MC9S08GB/GT Data Sheet, Rev. 2.

1.3 MCU Block Diagrams

These block diagrams show the structure of the MC9S08GB/GT MCUs.

Figure 1-1. MC9S08GBxx Block Diagram

PTD3/TPM2CH

PTD4/TPM2CH

PTD5/TPM2CH

PTD6/TPM2CH

PTC1/RxD PTC0/TxD

VSS

V (^) DD

PTE3/MISO PTE2/SS

PTA7/KBI1P7–

PTE0/TxD

PTE1/RxD

PTD2/TPM1CH PTD1/TPM1CH PTD0/TPM1CH

PTC PTC PTC PTC PTC3/SCL PTC2/SDA

PORT A

PORT C

PORT D

PORT E

8-BIT KEYBOARD INTERRUPT MODULE (KBI1)

IIC MODULE (IIC1)

SERIAL PERIPHERAL INTERFACE MODULE (SPI1)

USER FLASH

USER RAM (GB60 = 4096 BYTES)

DEBUG MODULE (DBG)

(GB60 = 61,268 BYTES)

HCS08 CORE

NOTES:

1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).

NOTE 1

NOTE 1

3-CHANNEL TIMER/PWM MODULE (TPM1)

PTB7/AD1P7– PORT B

PTE5/SPSCK PTE4/MOSI

PTE

PTE

INTERFACE MODULE (SCI2)

HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT

VOLTAGE REGULATOR

RTI

SERIAL COMMUNICATIONS

COP IRQ LVD

INTERNAL BUS

LOW-POWER OSCILLATOR

INTERNAL CLOCK GENERATOR (ICG)

RESET

VSSAD

V (^) DDAD

V (^) REFH V (^) REFL

ANALOG-TO-DIGITAL CONVERTER (ATD1)

INTERFACE MODULE (SCI1)

SERIAL COMMUNICATIONS

5-CHANNEL TIMER/PWM MODULE (TPM2)

PORT F

PTF7–PTF

NOTE 1

PTD7/TPM2CH

8 PTA0/KBI1P

8 PTB0/AD1P

8

PTG PTG2/EXTAL PTG0/BKGD/MS

PTG1/XTAL

PORT G

PTG

PTG

PTG PTG

NOTE 4

NOTES 1, 5

(GB32 = 32,768 BYTES)

(GB32 = 2048 BYTES)

IRQ NOTES 2, 3

10-BIT

NOTES 1, 6

NOTE 1

NOTES 1, 5

BDC CPU

Chapter 1 Introduction

MC9S08GB/GT Data Sheet, Rev. 2.

Figure 1-2. MC9S08GTxx Block Diagram

PTD3/TPM2CH

PTD4/TPM2CH

PTC1/RxD PTC0/TxD

VSS

V (^) DD

PTE3/MISO PTE2/SS

PTA7/KBI1P7–

PTE0/TxD

PTE1/RxD

PTD1/TPM1CH PTD0/TPM1CH

PTC6 (NOTE 6) PTC5 (NOTE 6) PTC PTC3/SCL PTC2/SDA

PORT A

PORT C

PORT D

PORT E

8-BIT KEYBOARD INTERRUPT MODULE (KBI1)

IIC MODULE (IIC1)

SERIAL PERIPHERAL INTERFACE MODULE (SPI1)

USER FLASH

USER RAM (GT60 = 4096 BYTES)

DEBUG MODULE (DBG)

(GT60 = 61,268 BYTES)

HCS08 CORE

NOTES:

1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. PTC[6:5] are not available on the 42-pin SDIP package.
7. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
8. Only two timer channels per TPM are bonded out. All channels are available for use as software compare.

NOTE 1

NOTE 1

3-CHANNEL TIMER/PWM MODULE (TPM1)

PTB7/AD1P7– PORT B

PTE5/SPSCK PTE4/MOSI

INTERFACE MODULE (SCI2)

HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT

VOLTAGE REGULATOR

RTI

SERIAL COMMUNICATIONS

COP IRQ LVD

INTERNAL BUS

LOW-POWER OSCILLATOR

INTERNAL CLOCK GENERATOR (ICG)

RESET

VSSAD

V (^) DDAD

V (^) REFH V (^) REFL

ANALOG-TO-DIGITAL CONVERTER (ATD1)

INTERFACE MODULE (SCI1)

SERIAL COMMUNICATIONS

5-CHANNEL TIMER/PWM MODULE (TPM2)

NOTE 1

8 PTA0/KBI1P

8 PTB0/AD1P

PTG2/EXTAL

PTG0/BKGD/MS

PTG1/XTAL PORT G

NOTE 4

NOTES 1, 5

(GT32 = 32,768 BYTES)

(GT32 = 2048 BYTES)

IRQ NOTES 2, 3

10-BIT

NOTES 1, 7

NOTE 1

(NOTE 8)

(NOTE 8)

BDC CPU

(GT16 = 16,384 BYTES)

(GT16 = 1024 BYTES)