Optimizing Performance with Sentinel Scheduling for VLIW and Superscalar Processors - Prof, Study Guides, Projects, Research of Electrical and Electronics Engineering

Sentinel scheduling, a method for optimizing performance on vliw (very long instruction word) and superscalar processors. The authors, s. Mahlke et al., present the concept in the context of a research paper published in asplos-5 in 1992. Topics such as code generation, memory hierarchy management, and cycle scheduling. Students may find this document useful for understanding the principles of processor scheduling and optimization.

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EECS 583 – Class 14
Superblock Scheduling
University of Michigan
March 7, 2005
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Download Optimizing Performance with Sentinel Scheduling for VLIW and Superscalar Processors - Prof and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity!

EECS 583 – Class 14 Superblock Scheduling

University of Michigan March 7, 2005

  • 1 -

Reading Material^ Y

Today’s class

Ā»^

ā€œThree Architectural Models for Compiler-ControlledSpeculative Executionā€, P. Chang et al., IEEE Transactions onComputers, Vol. 44, No. 4, April 1995, pp. 481-494.

Y^

Material for the next lecture^ Ā»

ā€œSentinel Scheduling for VLIW and Superscalar Processorsā€,^ S. Mahlke et al., ASPLOS-5, Oct. 1992, pp.238-

  • 3 -

Sample Projects (From Previous Semesters)^ Y

Analysis/opti

Ā»^

Compiler switch spacewalking

Ā»^

New hyperblock formation algorithm

Ā»^

Partial redundancy elimination

Ā»^

Control flow redundancy elimination via a BDD

Ā»^

Exposing branch correlation via code replication

Y^

Code gen^ Ā»

Register allocation in software pipelined loops Ā» Instruction scheduling for multiple threads Ā» Buffer overflow protection Ā» Automatic thread partitioning – control/data Ā» Compiler-directed voltage scaling Ā» TI C6x code generator

  • 4 -

Sample Projects (From Previous Semesters)^ Y

Memory

Ā»^

Data relocation to scratch pad (memory bandwidth)

Ā»^

Dynamic mapping of instructions to scratch pad (power)

Ā»^

Data layout optimization

Ā»^

Correlation-based prefetching

Ā»^

Software-controlled run-ahead prefetching

Ā»^

Structure field reorganization (Impact)

  • 6 -

Operation Priority^ Y

Priority – Need a mechanism to decide which ops toschedule first (when you have multiple choices) Y Common priority functions

Ā»^

Height – Distance from exit node^ y

Give priority to amount of work left to do

Ā»^

Slackness – inversely proportional to slack^ y

Give priority to ops on the critical path

Ā»^

Register use – priority to nodes with more source operands andfewer destination operands^ y

Reduces number of live registers

Ā»^

Uncover – high priority to nodes with many children^ y

Frees up more nodes

Ā»^

Original order – when all else fails

  • 7 -

Height-Based Priority^ Y

Height-based is the most common

Ā»^

priority(op) = MaxLstart – Lstart(op) + 1

0, 1

2, 2

1

0, 0

1 2 2

1 4, 4^2 6, 6

2

2

2

op
priority

2, 3

2

0, 5

4, 7

7, 7

(^1) 8, 8

  • 9 -

Cycle Scheduling Example

Machine: 2 issue, 1 memory port, 1 ALU Memory port = 2 cycles, non-pipelined ALU = 1 cycle

0, 1

RU_map
time ALU MEM 0 1 2 3 4 5 6 7 8 9

op^

priority 1

8 2

9 3

7 4

6 5

5 6

3 7

4 8

2 9

2 10

1

2m

2, 2

1

0, 0

1 3m

5m

1 2 2

1 4, 4^2 6, 6

2

2

2 2, 3 4

2

6

0, 5 7m 7, 7

4, 7

8

9 1 10

(^1) 8, 8

  • 10 -

Cycle Scheduling Example (2)

RU_map
Schedule

0, 1

time ALU MEM 0 1 2 3 4 5 6 7 8 9

2m

2, 2

1

0, 0

1 3m

5m

1 2 2

1 4, 4^2 6, 6

2

2

2

time Ready
Placed

2, 3 4

op^

priority 1

8 2

9 3

7 4

6 5

5 6

3 7

4 8

2 9

2 10

1

2

6

0, 5 7m 7, 7

4, 7

8

9 1 10

(^1) 8, 8

  • 12 -

Class Problem Machine: 2 issue, 1 memory port, 1 ALU Memory port = 2 cycles, pipelined ALU = 1 cycle

0, 1m

2m 0,

2

4m

6

1 1 1 1 1

2 3,4 5,

1

(^27)

2, 3

2,2 2

5 3,

4, 0,

8

9m

6, 10

1.^
Calculate height-based priorities
2.^
Schedule using cycle scheduler
  • 13 -

List Scheduling (Operation Scheduler)^ Y

Build dependence graph, calculate priority Y Add all ops to UNSCHEDULED set Y while (UNSCHEDULED not empty)

Ā»^

op = operation in UNSCHEDULED with highest priority

Ā»^

For time = estart to some deadline^ y

Op can be scheduled at current time? (are resources free?)

X^

Yes, schedule it, op.issue_time = time^ ±
Mark resources busy in RU_map relative to issue time ± Remove op from UNSCHEDULED

X^

No, continue

Ā»^

Deadline reached w/o scheduling op? (could not be scheduled)

X^

Yes, unplace all conflicting ops at op.estart, add them toUNSCHEDULED

X^

Schedule op at estart^ ±
Mark resources busy in RU_map relative to issue time ± Remove op from UNSCHEDULED
  • 15 -

Operation Scheduling Example (2)

0, 1 op^

pr 1

8 2

9 3

7 4

6 5

5 6

3 7

4 8

2 9

2 10

1

2m

2, 2

1

0, 0

Schedule

1 3m

5m

1 2 2

1 4, 4^2 6, 6

2

2

2

time Placed 0

2, 3 4

2

6

0, 5 7m

4, 7

7, 7

8

9 1 10

(^1) 8, 8

  • 16 -

Generalize Beyond a Basic Block^ Y

Superblock

Ā»^

Single entry

Ā»^

Multiple exits (side exits)

Ā»^

No side entries

Y^

Schedule just like a BB^ Ā»

Priority calculations needs change Ā» Dealing with control deps

  • 18 -

Operation Priority in a Superblock^ Y

Priority – Dependence height and speculative yield

Ā»^

Height from op to exit * probability of exit

Ā»^

Sum up across all exits in the superblock

1

3

Exit0 (25%)
12 Exit1 (75%)

1

op
Lstart
Lstart1 Priority

1

Priority(op) = SUM(Probi * (MAX_Lstart – Lstarti(op) + 1))

valid late times for op

  • 19 -

Dependences in a Superblock

Superblock
* Data dependences shown, all are reg flow except 1
Ɔ^
6 is reg anti
* Dependences define precedence ordering of operations to ensure correct execution semantics * What about control dependences? * Control dependences define precedence of ops with respect to branches
1: r1 = r2 + r32: r4 = load(r1)3: p1 = cmpp(r3 == 0)4: branch p1 Exit15: store (r4, -1)6: r2 = r2 – 47: r5 = load(r2)8: p2 = cmpp(r5 > 9)9: branch p2 Exit
Note: Control flow in red bold