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Module-X
Lecture-I
ATPG for Synchronous Sequential Circuits
1. Introduction
Till now we have been looking into VLSI testing, only from the context of combinational circuits. In this module we will study ATPG for sequential circuits. In the first lecture we will see the variations required in fault model, algebra and ATPG procedure in sequential circuits compared to combinational ones. Also we will compare the ATPG complexity in both the cases and show that testing sequential circuits is many folds more involved than testing combinational circuits. Following that in the next lecture we will introduce a special scheme called “scan chain” which ``modifies a sequential circuit into a virtual combinational one”. So, test patterns for a sequential circuit with scan chain can be generated with slight variation in ATPG algorithms for combinational circuits (D- algorithm, for example). In this lecture we will first discuss the difference between sequential and combinational circuits from the context of ATPG and single stuck-at fault model. In this course we will concentrate only on sequential synchronous circuits with a single clock.
2. ATPG and testing: Sequential versus combinational circuits
Let us first see the basic architecture of a sequential circuit in Figure 1. In the figure it may be noted that there are three blocks, namely NSF, OFB and state flip-flop. The first two blocks are combinational circuits and the state flip-flop has sequential elements. So ATPG procedure for the NSF and OFB blocks should be similar to the ones already introduced in the previous lectures. However, it may be noted that compared to a standard combinational circuit, in case of NSF some inputs (state feedback) are not controllable and its outputs are not observable. Similarly, in case of the OFB, some of its inputs are non-controllable. When a circuit powers up, the flip-flops can have any value (0 or 1). So for ATPG of the combinational blocks in sequential circuits, we need to
control (indirectly) the values in the nets which are outputs of flip-flops and observe (indirectly) the nets which are inputs to the flip-flops. Once indirect controllability and observability are achieved, ATPG for these combinational blocks (in sequential circuits) can be done using D-algorithm (or any other combinational APTG algorithm).
Next state function (NSF) (^) State flip flop
Output function block (OFB)
Primary inputs
Clock
Primary outputs
Secondary inputs (state feed back)
Secondary Outputs (NSF block outputs)
Figure 1. Basic architecture of a sequential circuit [1] Before we illustrate how indirect controllability and observability can be achieved in these combinational blocks, we will discuss some assumptions in ATPG for single clock sequential circuits. In single clock sequential circuits, each flip-flop is treated as 1-bit memory element with ONE common clock. For each primary input pattern and secondary input pattern (present state), the resulting primary output and secondary output (next state) patterns are produced. After a clock edge, the secondary output pattern (next state) is transferred to the output of the flip-flops (present state), which become new secondary inputs. Also, the primary outputs are updated. This activity occurs at each clock edge, and so it is called “synchronous” operation. Single stuck at faults are assumed in the two combinational blocks namely, NSF and OFB. Internal faults of flip-flops are not modeled; their output and input faults are modeled as faults on input and output signals of the combinational blocks. In other words, flip-flops are treated as ideal memory elements and no faults are considered in the clock signal. Most of the time, D-flip-flops are used in VLSI designs. So in this course whenever we refer to a flip-flop we essentially mean a D-flip-flop.
s-a- D Q
1 2
a= X
b= 0
c
d 0
e X
clock
D
primary output g X
f X
Figure 4. Indirect controlling of f to 0 After net f is made 0, then a =1 and b =X would propagate the fault effect (D) to the primary output; this is shown in Figure 5.
s-a- D Q
1 2
a=
b=X
c 0 d
e 0
clock
D
primary output g D
f 0
Figure 5. Test pattern for the s-a-0 fault So, it may be noted that ATPG for combinational blocks in sequential circuits require more than one pattern. In this example, the first pattern is a =X, b =0 and clock edge followed by a =1 and b =X. In such cases, final pattern is according to combinational ATPG (that sensitize the fault and propagates the effect to a primary output) and all other initial patterns are to bring the secondary inputs to their required value.
ATPG for a fault in the NSF block is more complex than the ones in the OFB. In case of a fault in the NSF we need to indirectly control the secondary inputs and in addition, propagate the fault effect to the primary output via OFB. This is illustrated using a s-a- fault at net c in the circuit (Figure 6). First, primary input b =0 ( a =X) and a clock edge is
applied; this makes e =0 (and also c =0) after the edge. It may be noted that even in
presence of the s-a-1 fault, b =0 and a clock edge makes c =0; this sensitizes the fault ( D
at c ). In the next step, b =1 ( a =X) and a clock edge would propagate the fault effect ( D ) to the output of the flip-flop (i.e, secondary input of the OFB). Finally, a =0 ( b =X) would propagate fault effect to the primary output. Above mentioned three steps are shown in Figure 6.
s-a-
D Q
1 2
a= X
b= 0
c
d 0
e X
clock g X
primary output
f X
s-a-
D Q
1 2
a= X
b= 1
c
d
e 0
clock g X
primary output
f (^0) D
D
s-a-
D Q
1 2
a= 0
b= X
c
d
e
clock primary output^ g
f X D^ D
D Figure 6. ATPG for s-a-1 fault in the NSF block
Now, we will see an interesting thing. If we use higher order algebra, then only one pattern can test the fault. Let us see the case if b =0 ( a =X). Fault is sensitized as D and e=f = D. Now as the secondary input ( c ) is not controlled, c =X. By 5 value algebra, d =X and so fault effect cannot be propagated to the output. However, if we observe carefully at net d, we will note that if the fault is there then d =X (as value is determined by the flip-flop at start up of circuit). However, if fault is not there then d =0 (as e =0). So we can mark d as 0/X. Now, f = D , which in turn makes g= D ; D (=0/1) OR 0/X = 0/1 (= D ). So fault can be detected using a single pattern b =0 ( a =X). All these steps are shown in Figure 9.
a= X^ D
b= 0
c X (^) d e
clock g f
Q 1 2 s-a-1 D D D
0/X
(0/X) OR ( D) = 0/
Figure 9. ATPG for s-a-1 fault using higher order algebra The following points are to be noted In the example, higher order algebra is used, as a net is marked as 0/X, which is not available in 5 value algebra. Higher order algebra improves efficiency of ATPG of sequential circuits. As higher order algebra reduces the number of input (primary and secondary) lines to be controlled, there is reduction in the number of steps (in terms of clock edges and test patters) to control the secondary inputs (or make the NSF block outputs observable via OFB). However, it does not guarantee that ATPG will not require controlling the secondary inputs and propagating the fault effect to the primary output via OFB. This example was a special case where controlling the secondary inputs were not required. Higher order algebra will also reduce the number of lines to be controlled in ATPG of a combinational circuit. However, it is not applied as computational complexity rises with increase in order of the algebra and inputs are easily controllable in combinational circuits.
Table 1 illustrates a 9 value algebra which is used for ATPG of combinational blocks in sequential circuits. Table 1. Nine value algebra Symbol Implication Normal Circuit Faulty Circuit 0 (0/0) 0 0 1 (1/1) 1 1 X (X/X) X X D (1/0) 1 0 (0/1) 0 1 G0 (0/X) 0 X G1 (1/X) 1 X F0 (X/0) X 0 F1 (X/1) X 1
a=
b=1 j
d 1
e 1
g 1
s-a- c=
h 0
i 1 k
D
D F
F
Figure 11. Sequential circuit of Figure 10 with flip-flops replaced by nets Before we study in detail the ATPG for the circuit given in Figure 10, we disuses the following definitions and conditions.
Definition 1: Sequential depth of a flip-flop: If the output of a flip-flop can be controlled by only primary inputs (and a clock pulse) it has sequential depth of 1. In the circuit of Figure 10, flip-flop F1 has sequential depth of 1 as it is controllable by primary input(s) c. A flip-flop has a sequential dept of dseq if its output is dependent on primary inputs and at least one flip-flop of depth dseq -1. In the example, flip-flop F2 is dependent on primary input b and output of flip-flop F1 (via net e ); so sequential depth of F2 is 2.
Definiation2: Non-cyclic Circuit A sequential circuit is non-cyclic if there is no flip-flop whose input is dependent on its output. For example, in the circuit of Figure 10, input of F1 is dependent on only primary inputs. On the other hand, input of F2 is dependent on primary inputs (net b ) as well as the output of F1 (net d ). So the circuit non-cyclic. An example of a cyclic sequential circuit is given in Figure 12. In this case input of F1 is dependent on its own output (and primary input). It may be noted that in cyclic circuits we may not be able to control the secondary inputs; this concept will be elaborated in an exercise problem. A flip-flop whose input is dependent on its own output is called a cyclic flip-flop.
D clock
Q F
primary output primary input Figure 12. Cyclic sequential circuit
Property 1. The secondary inputs of a cycle free sequential circuit of depth dseq can be brought to controllable value is at most dseq primary input patterns and clock pulses. Proof Idea: The proof is obvious. All flip-flops with dseq =1 can be controlled by setting primary inputs and a clock pulse. Now, as all flip-flops with dseq =1 have been set, we can control flip-flops with dseq =2 by setting primary inputs and a clock pulse. In this order, if there are flip-flops with dseq = n , we require at most n primary input patterns and n clock pulses. The proof idea for a circuit with dseq =2 is shown in Figure 13.
D clock
Q F
comb. ckt 1 primary input
D Q F clock
comb. ckt 2
dseq =1 dseq = Figure 13. Illustration of the proof idea of Property 1
Time Frame -dseq Time Frame -dseq^ +1 Time Frame 0
Primary inputs
Sequential circuit with flip-flops replaced by Secondaryinputs nets
Initialized to X
Primary outputs
Primary inputs
Sequential circuit withflip-flops replaced by nets
outputsSecondaryinputsSecondary outputsSecondary
Primary inputs
Sequential circuit with flip-flops replaced by nets
inputsSecondary
Figure 14. Time Steps for sequential ATPG using time frame expansion method
a=X b=X
F1=X
F2=X
c=1 a=X^ b=
F1=
c=1 a=1^ b=
F1=
F2=
c=X
Time Frame -2 Time Frame -1 Time Frame 0
F
F2=X F
d d^ d
i
i (^) i
h X
g X
j X/
k X
e X
j X/
k X
e 1
j (^) h 0
g 1
e 1
k
D
D
s-a-0 s-a-0 h s-a- X
g X
Figure 14. ATPG for the s-a-0 fault in the circuit of Figure 10: time frame expansion approach
Module-X
Lecture-II and III
Scan Chain based Sequential Circuit Testing
1. Introduction
In the last lecture we have seen that the major problem in testing (and ATPG) of sequential circuits is difficulty in controlling secondary inputs (i.e., outputs of flip-flops) and difficulty in observing secondary outputs (i.e., inputs of flip-flops). In this lecture we will discuss various techniques to make the flip-flops controllable and observable, which convert a sequential circuit into virtual combinational one. Following that ATPG for combinational circuits would suffice for sequential circuits. However, for achieving this, additional circuitry, called design for test (DFT), will be put on-chip, which would add to extra area overhead. In the next section we will explore different schemes to control and observe the flip-flops.
2. Controllability and observability of flip-flops 2.1. Set and reset lines One of the simplest way to directly control flip-flops is through set-reset lines. Set-reset lines can directly make the output of a flip-flop to be 1/0 without any input and clock pulse. A D flip-flop with set-reset lines is shown in Figure 1 and its functionality is shown in Table 1.
D Q
clock
set
reset
input
Figure 1. D-Flip-flop with set and reset
Table 1. Truth table for D flip-flop with set-reset lines Input (D) Output (Q) set reset clock Don’t care 1 1 0 Don’t care Don’t care 0 0 1 Don’t care Don’t care Illegal 1 1 Don’t care 1 1 0 0 Clock edge 0 0 0 0 Clock edge
From the truth table it may be observed that set (reset) lines makes the output 1(0) irrespective of input D and clock pulse. However, both the set and reset lines cannot be made high simultaneously. Also, when the D-flip-flop functions normally, both set and reset lines are kept low. Now we will see how use of this type of flip-flop helps in testing the circuit given in exercise of last lecture (Lecture 1, module 12). The circuit with a s-a-1 fault in the primary input line is shown in Figure 2 (a). Also, the flip-flop has set/reset lines. By D-algorithm, a test pattern would be: primary input =0, secondary input (other input of XOR gate)=0 and fault effect at primary output = D. So in Step-1 (Figure 2 (b)), set =1 and reset =0 (and and primary input =X); this makes output of flip-flop (i.e., secondary input) to be 1. In Step-2 (Figure 2 (c)), set =0,
reset =0 and primary input =0; this sensitizes fault location as D and its effect propagates to the input of the flip-flop as D. Also a positive clock pulse is applied which transfers D to output of the flip-flop (primary output). These two steps complete ATPG (and testing) of the fault. So it may be observed that the fault which was un-testable by time frame expansion method becomes testable using set/reset flip-flop. Further, one pattern is required to set/reset the flip- flops and another pattern (at primary inputs) is required to sensitize and propagate the fault effect to a primary output. So, unlike time frame expansion method where dseq +1 test patterns are required ( dseq patterns to initialize the flip-flops and one pattern to sensitize/propagate fault effects), in case of set/reset flip-flops only two patters are required (one to set or reset the flops and one to sensitize/propagate fault effects). This saving in number of test patterns (i.e., test time) is illustrated in the circuit example of Figure 10 of the last lecture. The circuit (Figure 10 of Lecture 1, module 12) with set/reset flip flops is shown in Figure 3(a).
a
b j
d
e
g
f
s-a- c
h
i D Q k
clock
set(F1)
reset(F1)
F
D Q
clock
set(F2)
reset(F2)
F
a=X b=X j e
g
f
s-a- c=X
h
D Q k
clock
set(F1)=
reset(F1)=
F
D Q
clock
set(F2)=
reset(F2)=
F
d 1
i 1
a= b=1 j e
g 1
f 1
s-a- c=X
h 0
D Q k
clock
set(F1)=
reset(F1)=
F
D Q
clock
set(F2)=
reset(F2)=
F
d 1
i 1
(a) Circuit
(b) Step-1: Flip-flops set
(c) Step-2: Test patten applied Fault effect propagated
D D
Figure 3. Testing using set/reset flip-flops: illustration of saving in test patterns
As discussed in the last lecture, three patterns were required to test the s-a-0 fault at net j: (i) a =X, b =X, c =1 and clock pulse (ii) a =X, b =1, c =1 and clock pulse and (iii) a =1, b =1, c =X. Also it is to be noted that dseq =2, for the circuit. Now, by using the set/reset flip-flops, we will see only two patterns are required to test the fault. By ATPG using D-algorithm, nets d and i are to be 1 for testing the fault. So both the flip-flops are set by the pattern: a =X, b =X, c =X, set (F1)=1, reset (F1)=0, set (F2)=1 and reset (F2)=0; this is shown in Figure 3(b). Finally, pattern a =1, b =1, c =X, set (F1)=0, reset (F1)=0, set (F2)=0 and reset (F2)=0 is applied to sensitize and propagate the effect of the fault to primary output; this is shown in Figure 3(c). So, only two patterns can test the fault. However the most important point is “Irrespective of the value of d (^) seq , only two patterns are required to test a sequential circuit with set/reset flip-flops”. The gain can be easily understood because any practical circuit has more than thousands of flip-flops. On the other hand, there is a big problem with the scheme that makes it impractical to be applied in a practical system. An input output block diagram of the circuit of Figure 3 is shown in Figure 4. It may be noted that it has 9 I/O pins (3 primary inputs + 1 primary output + 2 nffs set-reset lines, where n (^) ffs is the number of flip-flops and a clock).
The largest number of I/O pins supported in most complicated packages is about 1024. So, for a circuit with thousands of flip-flops, this approach requires a package of thousands of I/O pins (for the 2 nffs factor) with makes it impractical.
a
b c
clock
k
set(F1) set(F2)
reset(F1) reset(F2)
(primary output)
Figure 4. Input output block diagram of the circuit shown in Figure 3.
