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March 30, 2007 Page 1 of 4
Name:
Student Number:
- Check that your exam includes all 4 pages.
- PRINT your name and student number in the spaces above.
- Read all instructions and problems carefully. Points may be deducted for failure to follow instructions.
- Show ALL of your work on these pages. If you need extra space for a particular problem, write on the back of the previous page.
- You are NOT permitted to use notes, books, calculators, or other resources during this exam.
- This exam lasts for 50 minutes. Point values are listed for each problem to assist you in best using your time.
Problem 1. (16 points possible)
Problem 2. (18 points possible)
Problem 3. (16 points possible)
TOTAL. (50 points possible)
March 30, 2007 Page 2 of 4
Problem 1. (16 points)
A. (10 points) Each row in the table below lists a decimal value and its representation in both 6-bit sign-magnitude and 6-bit 2’s-complement binary formats. Complete the table, filling in the missing entries in each row.
Value (decimal)
6-bit sign-magnitude binary representation
6-bit 2’s-complement binary representation
19
1 0 0 1 1 0
1 0 1 0 1 0
0 0 1 1 0 1
B. (6 points) What range of integer values can be represented by each of the following representations? Also circle either 1 or 2, indicating the number of different patterns for the value zero in the indicated representation.
Patterns Representation Range of possible integer values for zero
8-bit unsigned: to 1 2
10-bit sign-magnitude: to 1 2
n-bit 1’s-complement: to 1 2
n-bit 2’s-complement: to 1 2
March 30, 2007 Page 4 of 4
Problem 3. (16 points)
A. (3 points) A loadable T (toggle) register that uses two-phase non-overlapping clocking is being designed. The logic symbol for this register is shown below, on the left. Complete the state table, on the right below, for this register. LD T Q
T D Q LD
1 2
B. (6 points) Complete the following timing diagram for this register. Assume that the initial value of the output, Q, is zero.
LD
T
D
Q
C. (7 points) A two-bit binary counter, implemented using these loadable T registers, is shown below. Complete the state table below for this counter, computing LD, T 1 , T 0 , and the next state. Finally, show the sequence of values generated by this counter, starting at <00>.
Q 1 Q 0 LD T 1 T 0 Q 1 +^ Q 0 + 0 0 0 1
1 0 1 1
1 1
1 2
T D Q LD
1 2
T D Q LD
0
Q (^1)
Q (^0) Sequence Generated:
