(3) Assume suitable additional data if required.
1. (?-) Perform the following operations without converting to any other base.
\.' (i) (FE6)H-(EFC)H
\ (ii) (3 2 4 )5X ( 2 1 )5
(iii) (5 1 2 )8 + ( 2 77 )8
"(b) Determine the truth table for the circuit shown below:
"'~
A
Bd
,
c'
,.:--.
(c) Convert SRflip-flop to D flip-flop.
(d) Implement following expression using only one 8:1 Multiplexer and few gates.
\. '\, F = ~m (2, 3, 5, 6, 8, 11, 13, 14, 15)
2. (a) Simplify the following equations using K Map.
(i) ABCD+ ABD+ABCD+ACD+ABC
- - -- -- -
(ii) A D + A B 0 + A CD + ACD
(b) Implement 32: 1 multiplexer using two :16:1 multiplexer and OR gates.
\
3. (a), Minimize the following expression using Quine McCluskey tabular method:
F(A, B, C, D)= ~m (1',3,5,10,11,12,13,14,15) .
(b) Implement the Gray code to BCD code converter using basic gates only.
4. (a). Design mod 10 asynchronous up counter with the help of necessary decoding logic.
r".' (b) Give the timing diagram for the counter of part (a).
(c) Explain how to convert the above counter to count down.
(d) If the delay of a single FF is ions what will be the maximum clock frequency.
(e) Is glitch problem exist for above counter? Discuss. .
(f) Implement mod 6 counter using following two blocks.
Gl-\<..
(9, (90
elk. ThOcl .3
Cou'Yl +e.r
6
4
5
5
10
10
10
10
5
3
3
3
3
3
5. (a1 Design a 3 bit synchronous 'even' counter to give sequence of even numbers. Using 10
D FF. Take care of lock out condition while designing.
(b) Desing Full Subtractor circuit using active high lip, active low Olp Decoder. 10
6. (a) Design 4 bit ring counter using JK-FF, draw the timing diagram for the same.
(b) Compare TTL and CMOS logic families.
7. (a)' Design one bit BCD adder using IC 7483.
(b) Write short notes on (any two) :-
(i) Code converters
(ii) Error detecting and correcting code (iii) ALU
(iv) Priority Encoder.
----
10
10
10
10
