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°c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering.
The FET Bias Equation
Basic Bias Equation
(a) Look out of the 3 MOSFET terminals and replace the circuits with Thévenin equivalent circuits as showin in Fig. 1.
Figure 1: Basic bias circuit.
(b) Solve the FET drain current equation for VGS.
VGS =
r ID K
+ VT O
(c) Write the gate-source loop equation in the gate-source loop and let IS = ID. VGG − VSS = VGS + IS RSS = VGS + IDRSS (d) Solve the loop equation for VGS. VGS = VGG − VSS − IDRSS (e) Equate the two expressions for VGS and rearrange the terms to obtain a quadratic equation in
ID.
IDRSS +
r ID K
− (VGG − VSS − VT O) = 0
(f) Let a = RSS , b = 1/
K, and c = − (VGG − VSS − VT O). In this case, the bias equation becomes
aID + b
p IC + c = 0
Use the quadratic equation to solve for
ID, then square the result to obtain
ID =
Ã
−b +
b^2 − 4 ac 2 a
Note that there is a second solution using the minus sign for the radical. This solution results in VGS < VT O, which is a non realizable solution. The desired solution is the one which gives the smaller value of ID. (e) Check for the active mode. For the active mode, VDS > VGS − VT O =
p ID/K. VDS = VD − VS = (VDD − IDRDD) − (VSS + IS RSS ) = VDD − VSS − ID (RDD + RSS )
Example 1
Figure 2: Circuit for Example 1.
VGG =
V +R 2 + V −R 1
R 1 + R 2
RGG = R 1 kR 2
VSS = V −^ RSS = RS VDD = V +^ RDD = RD
Example 2
Figure 3: Circuit for Example 2.
VGG = V +^
R 2
RD + R 1 + R 2
− ID
RD
RD + R 1 + R 2
R 2 RGG = (R 1 + RD) kR 2
VDD = V +^
R 1 + R 2
RD + R 1 + R 2
RDD = RDk (R 1 + R 2 )
VSS = 0 RSS = RS The gate-source loop equation is
V +^
R 2
RD + R 1 + R 2
− ID
RD
RD + R 1 + R 2
R 2 = VGS + IDRS
Figure 5: Circuit for Example 4.
Example 4
For M 1
VGG 1 = V +^
R 2
R 1 + R 2
RGG 1 = R 1 kR 2 VSS 1 = 0 RSS 1 = RS 1
VDD 1 = V +^ RDD 1 = RD 1
The loop equation for ID 1 is
V +^
R 2
R 1 + R 2
= VGS 1 + ID 1 RS
This and the equation for VGS 1 can be solved for ID 1. For M 2 VGG 2 = V +^ − ID 1 RD 1 RGG 2 = RD 1 VSS 2 = 0 RSS 2 = RS 2 VDD 2 = V +^ RDD 2 = RD 2
The loop equation for ID 2 is V +^ − ID 1 RD 1 = VGS 2 + ID 2 RS 2
This and the equation for VGS 2 can be solve for ID 2. Given ID 1 and ID 2 , it can be determined if the two MOSFETs are in the active mode.
Example 5
VGG 1 = V +^
R 2
R 1 + R 2
RGG 1 = R 1 kR 2 VSS 1 = 0 RSS 1 = RS 1
VGG 2 = IS 1 RS 1 RGG 2 = RS 1 VSS 2 = 0 RSS 2 = RS 2 VDD 2 = V +^ RDD 2 = RD 2 Let the currents to be solved for be ID 1 and ID 2 and let IS 1 = ID 1 and IS 2 = ID 2. The gate-source loop equation for ID 1 is
V +^
R 2
R 1 + R 2
= VGS 1 + ID 1 RS 1
This and the equation for VGS 1 can be solved for ID 1. The gate-source loop equation for ID 2 is
ID 1 RS 1 = VGS 2 + ID 2 RS 2
Given ID 1 and ID 2 , it can be determined if the two MOSFETs are in the active mode.
Figure 6: Circuit for Example 5.
