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Hard drive CPU Memory DVD Network
described in Appendix C
Recap – Computer Architecture
Device Controllers
Memory mapped I/O Direct Memory Access (DMA) Instruction Set Data transfer operations Arithmetic / logic operations Control flow instructions
controller controllerVideo^ controller controllerUSB
Outsideworld
controller
The architecture of the machine
Hard driveHard driveHard drive
Program counter
Instruction register
CPU Main memory Address Cells 00 01 02 03
FF
Registers Bus 0
1
2
F
Arithmetic / Logic Unit Control Unit
..... .....
Program Execution
“The machine cycle”
The composition of an instruction
for the machine in Appendix C
etucex^ E
De
co
d
F e
et
ch
- Fetch next instruction from memory (as indicated by the program counter) then increment the program counter.
- Decode the bit pattern in the instruction register.
- Execute the action requested by the instruction in the instruction register.
3 5 A 7
Op-code Operand
16-bit pattern
4-digit hexadecimal form
Performing the fetch step of the
machine cycle II
Decoding the instruction 35A
Program counter
Instruction register
A
156C
CPU Main memory
Address Cells A0 15 A1 6C A2 16 A3 6D
- Then the program counter is incremented so that it points to the next instruction.
Bus
Instruction (^) [ 3 5 A 7 [
Op-code 3 means
to store the contents
of a register in a
memory cell.
This part of the operand
identifies the register
whose contents are to be
stored.
This part of the operand
identifies the address of the
memory cell that is to
receive data.
Mnemonics
- It is hard to remember many numbers
- Use words associated with the numbers
jmpLE jmpLE reg<=R0,addr
jmp jmp addr
rotate right ror reg, num
bitwise XOR xor reg, reg, reg
jmpEQ halt jmpEQ reg=R0,adr
bitwise AND and reg, reg, reg
bitwise OR or reg, reg, reg
floating point addition addf reg, reg, reg
integer addition addi reg, reg, reg
move move reg1, reg
indirect store store reg, [reg]
direct store store reg, [addr]
indirect load load reg, [reg]
direct load load reg, [addr]
immediate load load reg, addr
db org
Instruction [ 3 5 A 7
[
Store
R
[0xA7]
store R5, [0xA7] <=> 35A
CQ I
Assembly II
or reg1,reg2,reg
and reg1,reg2,reg
xor reg1,reg2,reg
1. Both Contain 0
2. 0xfe contains 0,0xff contains 04
3. 0xfe contains 0, 0xff contains 05
4. I don’t know
bitwise or
bitwise and
bitwise exclusive or
load R1, 00100110b ;
load R2, 11111111b ;
load R0, 00000000b ;
and R3,R1,R2 ;
and R4,R1,R0 ;
or R5,R1, R2 ;
or R6, R1, R0 ;
xor R7,R1, R2 ;
halt ;
Program to demonstrate the basic bit-wise constructs
CQ II
4. I don’t know
