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A solution for implementing a datapath for a single machine language statement that combines the work of two statements, specifically for the lw and addi instructions, with a modification for the revised printing. It includes the addition of a new mux, control signal, and second write port to the register file, as well as a new adder for auto-incrementing the address.
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Key hw # 5.2 For full credit one only needs to get the bold entrees correct. Since in this chapter those are the ones we are emphasizing. lw, sw,add,sub,and,or,slt,beq, and j. a. With regwrite stuck at 0, we never write into a register. Will not work: add , addi, addu, and , andi, jal,lbu, lui, lw , nor, or , ori, slt , slti, sltiu, sltu, sll, srl, sub and subu. Looking at the greensheet, these instruction all need to make an assignment to a register. The rest will work b. If ALUOp 0 is stuck at zero then from figure 1.18, beq cannot work. Everything else can work. The aluop pair is used to send information to the ALU control about the instruction. beq is the only instruction that requires a one in the low order bit. c. If ALUOp 1 is stuck at zero then from figure 1.18, the R format instructions cannot work. Everything else will work. If the high order bit of aluop cannot be one then the correct signal cannot be sent to the alu control for R format instructions. d. If Branch is stuck at zero then the beq cannot work. From fig 3.17 if the branch control is zero, then the control input to the branching MUX is 0 and PC + 4 becomes the new PC value so the branch can never be taken. Actually this is OK if the branch is not supposed to be taken ie if the output of the ALU is not zero. So it would still work correctly sometimes. All other instructions still work. e. If MemRead is stuck at zero then memory never performs a read operations, thus the load operations will not work including lw. The other instructions will still work. f. If MemWrite is stuck at zero then we can never do a store operation and sw will not work. All operations that do not store in memory will work.
For the jr instruction we need to get the data from the read data 1 line to be stored in the PC. One way this can be accomplished by inserting a new MUX into the input line for the PC after any MUXs that might already be there. Insert a new control signal called rj and require that when rj is zero the previous value is passed through to the PC and when rj is one the value from read data 1 is passed through.
5.11. From the older version of the textbook we have the following solution. The problem is to provide a datapath for a single machine language statement that essentially does the combined work of the following two statements. The version in the revised printing will be addressed after this solution. lw $rs, L($rt) addi $rt, $rt, 1 // some texts may increment by 4 but that is a minor // change Note that the problem reverses the usual roles of rs and rt on the green sheet. For the machine language of the load $rs plays the usual role of rt, ie the register being loaded with a value from memory. Thus the ML for the new l_inc looks like Opcode $rt $rs immediate And $rt becomes the address for read reg 1. A modification is required to figure 5.17 to perform the autoincrement by adding 1 ( it should have been 4 (why?) to the contents or $rt. This new adder looks exactly like the one used for the PC (either 1 or 4 is acceptable for the increment). Then connect the output of Read data 1 to this new adder as an input. We also need to add a second write port to the register file, and required inputs write register 2 (wreg 2) and write data 2 (wdata 2) for this port. We also need a new control signal which we will call rr2. When rr2 is 1 we write using the new port. The output of the new adder connects to wdata2 and we need to connect the $rt value which is in instruction bits [25-21] to the sreg2 input. That should do it. We are very dependent on the books constraint that the register updates will be made at the end of the cycle for the single cycle machine for this to work. Instruction RgD ALSrc Memto- Reg Rg Wrt
Rd
Wrt Br AOp1 ALUp0 rr R-frmt 1 0 0 1 0 0 0 1 0 0 lw 0 1 1 1 1 0 0 0 0 0 sw X 1 X 0 0 1 0 0 0 0 beq X 0 X 0 0 0 1 0 1 0 l_inc 0 1 1 1 1 0 0 0 0 1