Compiler
Construction
Lecture 3
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Compiler Construction: Syntax Trees and the Back End, Cheat Sheet of Compiler Construction
An overview of the key concepts in compiler construction, focusing on syntax trees and the back-end of the compilation process. It discusses the use of abstract syntax trees (asts) as a more concise representation of the grammatical structure of a program, compared to the full parse tree. The document then delves into the various stages of the back-end, including instruction selection, register allocation, and instruction scheduling. It highlights the challenges and complexities involved in these tasks, such as the np-completeness of optimal register allocation and instruction scheduling. The document serves as a valuable resource for students and researchers interested in understanding the inner workings of compilers and the techniques used to generate efficient machine code from high-level programming languages.
Typology: Cheat Sheet
2023/2024
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Compiler
Construction
Lecture 3
Syntax Tree
x+2-y goal expr op^ term expr expr op term term
- <id,y> <id,x> + <number, 2>
Abstract Syntax Trees
(^) This is much more concise
<id,y>
<id,x> <number,2> +
Abstract Syntax Trees
- (^) AST summarizes grammatical structure without the details of derivation - <id,y> <id,x> <number,2> +
Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
- (^) Translate IR into target machine code.
- (^) Choose machine (assembly) instructions to implement each IR operation
Instruction Selection:
- Produce fast, compact code. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Instruction Selection:
- (^) Take advantage of target features such as addressing modes. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Instruction Selection:
- Spurred by PDP-11 to VAX-11 - CISC. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Instruction Selection:
- RISC architecture simplified this problem. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Register Allocation:
- Manage a limited set of resources
- register file. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Register Allocation:
- (^) Can change instruction choices and insert LOADs and STOREs. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Instruction Scheduling:
- Avoid hardware stalls and interlocks. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling
IR IR
Instruction Scheduling:
- Use all functional units productively. Instruction selection IR (^) machine code errors Register allocation Instruction scheduling