Computer Organization II: Instruction Execution and Addressing Modes, Lecture notes of Computer Architecture and Organization

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Instruction sets

( Käskykannat )

Ch 10-11 [Sta10] „ Operations „ Operands „ Operand references (osoitustavat) „ Pentium / ARM

Lecture 6

Instruction cycle

„ CPU executes instructions “one after another”

„ Execution of one instruction has several phases (see state

diagram). The CPU repeats these phases

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(Sta10 Fig 10.1)

Computer Instructions ( konekäskyt )

„ Instruction set ( käskykanta ) =

„ Set of instructions CPU ‘knows’

„ Operation code ( käskykoodi )

„ What does the instruction do?

„ Data references ( viitteet ) – one, two, several?

„ Where does the data come for the instruction?

• Registers, memory, disk, I/O „ Where is the result stored?
• Registers, memory, disk, I/O

„ What instruction is executed next?

„ Implicit? Explicit?

„ I/O?

„ Memory-mapped I/O € I/O with memory reference operations

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Covered on Comp. Org I

Access time? Access rate?

Instructions and data ( käskyt ja data )

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instructions

data

address

value

Symbolic

name

(Sta10 Fig 11.13)

What kind of data?

„ Integers, floating-points

„ Boolean ( totuusarvoja )

„ Characters, strings

„ IRA (aka ASCII), EBCDIC

„ Vectors, tables

„ N elements in sequence

„ Memory references

„ Different sizes

„ 8 /16/32/ 64b, … „ Each type and size has its own operation code

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IBM EAS/390 (Sta10 Table 10.5)

Instruction representation ( käskyformaatti )

„ How many bits for each field in the instruction?

„ How many different instructions? „ Maximum number of operands per instruction? „ Operands in registers or in memory? „ How many registers?

„ Fixed or variable size ( vakio vai vaihteleva koko )?

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(Sta10 Table 10.1)

How many registers?

„ Minimum 16 to 32

„ Work data in registers

„ Different register (sets) for different purpose?

„ Integers vs. floating points, indices vs. data, code vs. data „ All sets can start register numbering from 0 „ Opcode determines which set is used

„ More registers than can be referenced?

„ CPU allocates them internally

• Register window – virtual register names „ Example: function parameters passed in registers
• Programmer thinks that registers are always r8-r15,
• CPU maps r8-r15 somewhere to r8-r
• (We’ll come back to this later)

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Architectures

„ Accumulator-based architecture ( akkukone ) „ Just one register, accumulator, implicit reference to it

„ Stack-based ( pinokone) „ Operands in stack, implicit reference „ PUSH, POP

„ Register-based ( yleisrekisterikone ) „ All registers of the same size „ Instructions have 2 or 3 operands

„ Load/Store architecture „ Only LOAD/STORE have memory refs „ ALU-operations have 3 regs

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LOAD R3, C

LOAD R2,B

ADD R1,R2,R

STORE R1,A

See : Appendix 10A in Ch10 [Sta10]

Example: JVM

Data alignment ( kohdentaminen )

„ 16b data starts with even ( parillinen ) (byte)address

„ 32b data starts with address divisible ( jaollinen ) by 4

„ 64b data starts with address divisible by 8

„ Aligned data is easier to access

„ 32b data can be loaded by one operation accessing the word address ( sanaosoite )

„ Unaligned data would contain no ’wasted’ bytes, but

„ For example, loading 32b unaligned data requires two loads from memory (word address) and combining it

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load r1, 2(r4) shl r1, = load r2, 4(r4) shr r2, = or r1, r

load r1, 0(r4) or

r1: 11 22 33 44 r1: 11 22 33 44

r

r

Computer Organization II

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Memory references

(Muistin osoitustavat)

Ch 11 [Sta10]

Where are the operands?

„ In the memory „ Variable of the program, stack ( pino ), heap ( keko )

„ In the registers „ During the instruction execution, for speed

„ Directly in the instruction „ Small constant values

„ How does CPU know the specific location? „ Bits in the operation code „ Several alternative addressing modes allowed

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Addressing modes ( osoitusmuodot )

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(Sta10 Fig 11.1)

More addressing modes

„ Autoincrement (before/after)

„ Example CurrIndex=i++;

„ Autodecrement (before/after)

„ Example CurrIndex=--i;

„ Autoincrement deferred

„ Example Sum = Sum + (*ptrX++);

„ Autoscale

„ Example Double X; …. X=Tbl[i];

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EA = (R), R m (R) + S

EA = Mem(R), R m (R) + S

R m (R) - S, EA = (R)

operand size

EA = A + (R) * S

Computer Organization II

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Pentium

Pentium: Registers

„ General registers ( yleisrekisterit ), 32-b

„ EAX, EBX, ECX, EDX accu, base, count, data „ ESI, EDI source & destination index „ ESP, EBP stack pointer, base pointer

„ Part of them can be used as16-bit registers

„ AX, BX, CX, DX, SI, DI, SP, BP

„ Or even as 8-bit registers

„ AH, AL, BH, BL, CH, CL, DH, DL

„ Segment registers 16b

„ CS, SS, DS, ES, FS, GS

• code, stack, data, data, ...

„ Program counter ( käskynosoitin)

„ EIP Extended Instruction Pointer

„ Status register

„ EFLAGS

• overflow, sign, zero, parity, carry,…

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(Sta10 Fig 12.3c)

x86: Data types

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(Sta10Table 10.2)

Single / Double / Extended precision

„ Not aligned „ Little Endian

IEEE 754 standard

Pentium: Addressing modes (muistin osoitustavat)

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(Sta10 Table 11.2)

1, 2, 4, 8B

Registers: 1, 2, 4, 8B

Operand = (R)

x86 Addressing

indexing arrays? arrays in stack? two dimensional arrays?

Pentium: Addressing Mode Calculation

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(Sta10 Fig 11.2)

LA = (SR)+(I)*S+(B)+A

A

B

C

Discussion?

Pentium: Instruction format

„ CISC

„ Complex Instruction Set Computer

„ Lots of alternative fields

„ Part may be present or absent in the bit sequence „ Prefix 0-4 bytes „ Interpretation of the rest of the bit sequence depends on the content of the preceding fields

„ Plenty of alternative addressing modes ( osoitustapa)

„ At most one operand can be in the memory „ 24 different

„ Backward compatibility

„ OLD 16-bit 8086-programs must still work

• How to handle old instructions: emulate, simulate?

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only op-code always!

Pentium: Instruction format

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Addressing

1. Operand

(register)

2. operand (register)

or form part of the addressing-mode

(Sta10 Fig 11.9)

Pentium: Instruction format

„ Displacement (optional)

„ Certain addressing modes need this

„ 0, 1, 2 or 4 bytes (0, 8, 16 or 32 bits)

„ Immediate (optional)

„ Certain addressing modes need this, value for

operand

„ 0, 1, 2 or 4 bytes

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Computer Organization II

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ARM Instructions

ARM: Instruction set (käskykanta)

„ RISC

„ Reduced Instruction Set Computer

„ Fixed instruction length (32b), regular format

„ All instructions have the condition code (4 bits)

„ Small number of different instructions

„ Instruction type (3 bit) and additional opcode /modifier (5 bit) „ Easier hardware implementation, faster execution „ Longer programs?

„ Load/Store-architecture

„ 16 visible general registers (4 bits in the instruction)

„ Fixed data size

„ Thump instruction set uses 16 bit instructions

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ARM Data Types

„ 8 (byte), 16 (halfword), 32 (word) bits - word aligned

„ Unsigned integer and twos-complement signed integer

„ Majority of implementations do not provide floating-

point hardware

„ Little and Big Endian supported „ Bit E in status register defines which is used

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ARM Load/Store Multiple Addressing

„ Load/store subset of general-purpose registers

„ 16-bit instruction field specifies list of registers „ Sequential range of memory addresses „ Base register specifies main memory address

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(Sta10 Fig 11.4)

ARM Instruction Formats

„ S = For data processing instructions, updates condition codes „ S = For load/store multiple instructions, execution restricted to supervisor mode „ P, U, W = distinguish between different types of addressing mode „ B = Unsigned byte (B==1) or word (B==0) access „ L = For load/store instructions, Load (L==1) or Store (L==0) „ L = For branch instructions, is return address stored in link register Computer Organization II, Autumn 2010, Teemu Kerola 10.11.2010 38

(Sta10 Fig 11.10)

Discussion?

ARM Condition codes

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Condition flags:

N, Z, C and V

N – Negative

Z – Zero

C – Carry

V – oVerflow

(Sta10 Tbl 10.12)

RISC vs. CISC

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HW (Pentium) SW (Crusoe)

We’ll return to this later (lecture 8)

RISC

easy to execute

HW

CISC

support high-level languages

difficult to execute

HW

High-level programming language

High-level programming language

HW

CISC

support high-level lang

difficult to execute

RISC

easy to execute

High-level programming language