Analogue and Digital Electronics Exam Questions for Electronic Engineering Students, Exams of Digital Electronics

Exam questions from the analogue and digital electronics module of the bachelor of engineering (honours) in electronic engineering program at cork institute of technology. The questions cover topics such as mosfet current expressions, small signal gain calculations, and cmos amplifier analysis. Students are required to answer questions related to circuit analysis, voltage and current calculations, and transfer function gain and phase. The document also includes diagrams and specifications for various components.

Typology: Exams

2012/2013

Uploaded on 03/30/2013

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Cork Institute of Technology
Bachelor of Engineering (Honours) in Electronic Engineering - Stage 3
(EELXE_8_Y3)
Spring 2008
Analogue and Digital Electronics
(Time: 3 Hours)
Instructions
Answer FIVE (5) questions, at least two (2)
from each section.
All questions carry equal marks.
Requirements: 6-decade Log/Lin Graph Paper)
Examiners: Mr. P. Collins
Dr. B.V. Donovan
Prof. W.G. Hurley
Dr. S. Foley
Section A
Q1.
Assume that for the transistors in this question Kp = 20µA/V2, Vto = +1V for the n-channel
MOSFETs, Vto = -1V for the p-channel MOSFETs, lambda = 0.
a) Write expressions for the current in an N-channel MOSFET - one for the linear region of
operation and one for saturated operation. Write similar expressions for a P-channel device.
What terminal voltage conditions determine the operating region for both devices?
[2 Marks]
b) Calculate the currents flowing in M1 and M2 in Figure Q1a? [4 Marks]
W=20u
L=1u
M1
W=10u
L=1u
M2
V3
2V
V1
5V
V2
2V
Fig Q1a.
pf3
pf4
pf5
pf8
pf9

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Cork Institute of Technology

Bachelor of Engineering (Honours) in Electronic Engineering - Stage 3

(EELXE_8_Y3)

Spring 2008

Analogue and Digital Electronics

(Time: 3 Hours)

Instructions Answer FIVE (5) questions, at least two (2) from each section. All questions carry equal marks.

Requirements: 6-decade Log/Lin Graph Paper)

Examiners: Mr. P. Collins Dr. B.V. Donovan Prof. W.G. Hurley Dr. S. Foley

Section A

Q1.

Assume that for the transistors in this question Kp = 20μA/V^2 , Vto = +1V for the n-channel MOSFETs, Vto = -1V for the p-channel MOSFETs, lambda = 0.

a) Write expressions for the current in an N-channel MOSFET - one for the linear region of operation and one for saturated operation. Write similar expressions for a P-channel device. What terminal voltage conditions determine the operating region for both devices? [2 Marks]

b) Calculate the currents flowing in M1 and M2 in Figure Q1a? [4 Marks]

W=20u L=1u M

W=10u L=1u M

V V1 2V 5V

V 2V

Fig Q1a.

c) What is the voltage at node OUT in Figure Q1b? [ 4 Marks ]

W=20u L=1u M

R

W=10u 20k L=1u M

V

V1 2V

5V

V

2V

Out

Fig Q1b.

d) What is the voltage at node OUT in fig Q1c? [ 10 Marks ]

W=20u L=1u M

W=10u L=1u M

V

V1 2V

5V

V

2V

Out

W=10u L=10u M

Fig Q1c.

Q3.

Assume that for the transistors in this question Kp = 20μA/V^2 , Vto = +1V for the n-channel MOSFETs, Vto = -1V for the p-channel MOSFETs , lambda = 0.02.

For the CMOS amplifier shown in Figure Q3 assume that the poles are given by 1 18 1 2 1 2 18 20

M OUT OUT M

P

gm R R C P gm C

The zero is given by 18 (^21)

Z gm^ M

π C

= − if R 1 = 0.

a) Draw a simplified small signal model for the CMOS amplifier shown in Figure Q3. Explain the origins of the components in the model. [4 Marks]

b) With R 1 = 0Ω calculate the poles and the zero, and then draw a Bode plot for the amplifier. Use 6 decade log-linear paper with a frequency scale of 100Hz to 100MHz. Include on your answer script a written description of all turning points on the Bode plot along with the slopes of any lines. [8 Marks]

c) Repeat this exercise for R 1 = 1 /gmM18. [4 Marks]

d) From the Bode plots, what is the phase margin for this amplifier when used in a unity gain configuration? Calculate this for R 1 = 0Ω and for R 1 = 1 /gmM18. Which value of phase margin is better and why? [4 Marks]

80uA

W=10uL=1u MbreakPM

W=20uL=1u MbreakN M

W=20u MbreakNL=1u M

5V

W=10uL=1u MbreakPM

2.5V

2.5V

W=20uL=1u MbreakPM

W=20uL=1u MbreakN M

W=20uL=1u MbreakNM

W=20uL=1u MbreakN M

C 0.5pF 0.5pFC

R

Fig Q

Q5. Sketch a simplified Block diagram of either a Boost or Inverting (Buck/Boost) voltage converter and give a brief description of its operation, paying particular attention to the voltage waveforms at the output side of the Inductor. [5 Marks]

Referring to the simplified diagram of the Buck converter below (Fig Q5a), draw exact diagram of the (steady state) current flowing through the Inductor for a 5 Ohm load [5 Marks]

At what load does this converter become discontinuous and what would be the possible consequences? [4 Marks] Estimate the efficiency of this converter, for the conditions shown, if the components have the following specifications: RDS (on) of the SW1 = 10 mΩ, R (^) inductor = 20mΩ, Vdiode = 400 mV (1A) Ignore switching losses. Show all calculations clearly. [6 Marks]

Ohms Raw DC

PWM Control

25V 5V

Sw 1 L = 15 uH

D C

F =40 kHz

Fig Q 5a

Q6. Write a brief note, itemising the advantages of using F-to-V/V-to-F converters, as a medium for reliable data acquisition. [4 Marks]

Identify at least two environments where the technique is advantageous, [2 x 2 Marks] And show how appropriate ‘cabling’ would ensure reliability in both cases. [2 x 2 Marks]

The circuit below (Fig Q6a) is a simple voltage-to-(Pulse Repetition Rate) converter. Describe its principle of operation with appropriate Oscillograms/waveforms assuming that the switching thresholds for the CMOS gates is 0.5Vcc.

[5 Marks] Estimate values for the Three resistors ( Re, Rs and R ) to satisfy the Input/output relationship shown , for a pulse length of about 70us. [3 Marks]

I Vin

Re

V =^ V (^) in

+v cc

  • v cc

z

Cf (0.1uF)

R 10R

Vcc

R

s (^) s

I Charge = I/ 0.01uF

Fig Q6a

(5V)

Fout = 5 kPulses/s