Transmit Works - Advanced System Programming - Lecture Slides, Slides of Computer Applications

Main points are: Transmit Works, List of Buffer-Descriptors, Random Access Memory, Registers’ Names, Circular Buffer, Descriptor Control, Transmit Control, Configuration Word, Suggested C Syntax, Bit-Mask Definitions

Typology: Slides

2012/2013

Uploaded on 04/17/2013

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How ‘transmit’ works
descriptor0
descriptor1
descriptor2
descriptor3
0
0
0
0
Buffer0
Buffer1
Buffer2
Buffer3
List of Buffer-Descriptors
We setup each data-packets that we want
to be transmitted in a ‘Buffer’ area in ram
We also create a list of buffer-descriptors
and inform the NIC of its location and size
Then, when ready, we tell the NIC to ‘Go!’
(i.e., start transmitting), but let us know
when these transmissions are ‘Done’ Random Access Memory
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How ‘transmit’ works

descriptor

descriptor

descriptor

descriptor

Buffer

Buffer

Buffer

Buffer

List of Buffer-Descriptors

We setup each data-packets that we want to be transmitted in a ‘Buffer’ area in ram

We also create a list of buffer-descriptors and inform the NIC of its location and size

Then, when ready, we tell the NIC to ‘Go!’ (i.e., start transmitting), but let us know when these transmissions are ‘Done’

Random Access Memory

Registers’ Names

Memory-information registers

TDBA(L/H) = Transmit-Descriptor Base-Address Low/High (64-bits)

TDLEN = Transmit-Descriptor array Length

TDH = Transmit-Descriptor Head

TDT = Transmit-Descriptor Tail

Transmit-engine control registers

TXDCTL = Transmit-Descriptor Control Register

TCTL = Transmit Control Register

Notification timing registers

TIDV = Transmit Interrupt Delay Value

TADV = Transmit-interrupt Absolute Delay Value

Tx-Descriptor Control (0x3828)

0 0 0 0 0 0 0

G

R

A

N

WTHRESH

(Writeback Threshold)

FRC

DPLX

FRC

SPD 0

HTHRESH

(Host Threshold)

I

L

O

S

A

S

D

E

L

R

S

T

PTHRESH

0 0 (Prefetch Threshold)

Recommended for 82573: 0x01010000 (GRAN=1, WTHRESH=1)

“This register controls the fetching and write back of transmit descriptors. The three threshhold values are used to determine when descriptors are read from, and written to, host memory. Their values can be in units of cache lines or of descriptors (each descriptor is 16 bytes), based on the value of the GRAN bit (0=cache lines, 1=descriptors). When GRAN = 1, all descriptors are written back (even if not requested).” --Intel manual

Transmit Control (0x0400)

R

R

R

MULR TXCSCMT UNORTX RTLC R

SW XOFF

COLD (upper 6-bits) (COLLISION DISTANCE)

COLD (lower 4-bits)

(COLLISION DISTANCE) 0 ASDV

I

L

O

S

S

L

U

TBI

mode

P

S

P

0 0 R

R

E

N

SPEED

CT

(COLLISION THRESHOLD)

EN = Transmit Enable SWXOFF = Software XOFF Transmission

PSP = Pad Short Packets RLTC = Retransmit on Late Collision

CT = Collision Threshold (=0xF) UNORTX = Underrun No Re-Transmit

COLD = Collision Distance (=0x3F) TXCSCMT = TxDescriptor Minimum Threshold

MULR = Multiple Request Support

82573L

Legacy Tx-Descriptor Layout

special

0x

0x

0x

CMD

Buffer-Address high (bits 63..32)

Buffer-Address low (bits 31..0)

CSO Packet Length (in bytes)

CSS status

reserved

Buffer-Address = the packet-buffer’s 64-bit address in physical memory

Packet-Length = number of bytes in the data-packet to be transmitted

CMD = Command-field CSO/CSS = Checksum Offset/Start (in bytes)

STA = Status-field

Suggested C syntax

typedef struct {

unsigned long long base_addr;

unsigned short pkt_length;

unsigned char cksum_off;

unsigned char desc_cmd;

unsigned char desc_stat;

unsigned char cksum_org;

unsigned short special;

} tx_descriptor;

TxDesc Status field

reserved

=0 LC^ EC^ DD

DD = Descriptor Done

this bit is written back after the NIC processes the descriptor provided the descriptor’s RS-bit was set (i.e., Report Status)

EC = Excess Collisions

indicates that the packet has experienced more than the maximum number of excessive collisions (as defined by the TCTL.CT field) and therefore was not transmitted. (This bit is meaningful only in HALF-DUPLEX mode.)

LC = Late Collision

indicates that Late Collision has occurred while operating in HALF-DUPLEX mode. Note that the collision window size is dependent on the SPEED: 64-bytes for 10/100-MBps, or 512-bytes for 1000-Mbps.

Bit-mask definitions

enum {

DD = (1<<0), // Descriptor Done

EC = (1<<1), // Excess Collisions

LC = (1<<2), // Late Collision

EOP = (1<<0), // End Of Packet

IFCS = (1<<1), // Insert Frame CheckSum

IC = (1<<2), // Insert CheckSum as per CSO/CSS

RS = (1<<3), // Report Status

DEXT = (1<<5), // Descriptor Extension

VLE = (1<<6), // VLAN packet

IDE = (1<<7) // Interrupt-Delay Enable

};

Network MTU

• Unless the ‘Large-Send’ functionality has

been enabled, there will be a maximum

length for your network ‘datagrams’ equal

to 1536 bytes (=0x0600)

• So if you reused the same Packet-Buffer

for successive transmissions, you could fit

your packet-buffer and a moderate-sized

Descriptor-Buffer into one 4KB-pageframe

Single page-frame option

Packet-Buffer (3-KB)

(reused for successive transmissions)

4KB

Page-

Frame

Descriptor-Buffer (1-KB)

(room for up to 256 descriptors)

Initialization

• Your device-driver needs to initialize your

82573L hardware to a known state, and

configure its options for your desired mode

of operation

• The Device Control register has bits which

let you initiate a ‘device reset’ operation

• The Device Status register has bits which

inform you when a ‘reset’ has completed

Device Status (0x0008)

GIO Master EN

PHY reset ASDV

I

L

O

S

S

L

U

TX

OFF 0 0

F D

Function ID

L U

SPEED

FD = Full-Duplex

LU = Link Up

TXOFF = Transmission Paused

SPEED (00=10Mbps,01=100Mbps, 10=1000Mbps, 11=reserved)

ASDV = Auto-negotiation Speed Detection Value

82573L

some undocumented functionality?

Extended Control (0x0018)

R

R

ITCE R

IAME R

DF

PAR

EN

PB

PAR

EN

Tx

LS

Tx LS Flow =

R

Phy Pwr Down En

DMA

Dyn GE

R

RO

DIS

R

SPD

BYPS

R

EE

RST

ASD

CHK

R

R

R

R

R

R

R

R

0 0 R

R

R

82573L

R

ASDCHK = AutoSpeed Detection Check TxLSFlow = Tx Large-Send Flow EERST = EEPROM Reset TxLS = Tx Large-Send functionality SPDBYPS = Speed-selection Bypass PBPAREN = Packet-Buffer Parity-Error Detect RODIS = Relaxed-Ordering Disable DFPAREN = Descriptor-FIFO Parity-Error Detect DMADynGE = DMA Dynamic-Gating Enable IAME = Interrupt-Acknowledge Auto-Mask Enable PhyPwrDownEn = Phy PowerDown Enable ITCE = Interrupt Timers Cleared Enable

Example

// clear STATUS bit

iowrite32( 0x00000000, io + E1000_STATUS );

// initiate Device-Reset and Phy-Reset

iowrite32( 0x84000000, io + E1000_CTRL );

// wait until STATUS bit #31 is set

while ( ( ioread32( io + E1000_STATUS )&(1<<31)) == 0 );

// program Link Up with desired operating-mode settings

iowrite32( 0x00040241, io + E1000_CTRL );

// wait until LU-bit in STATUS is set

while ( ( ioread32( io + E1000_STATUS )&(1<<10)) == 0 );