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Cork Institute of Technology
Bachelor of Engineering (Honours) in Mechanical Engineering- Stage 2
(NFQ Level 8)
Autumn 2007
Electrical & Electronic Engineering
(Time: 3 Hours)
Instructions Answer SIX questions – three from each section. Use separate answer books for each Section.
Examiners: Dr. R. A. Guinee Mr. P. Collins Mr. P. Clarke Prof. M. Gilchrist
Section A
Q1. (a) Draw the ANSI symbol for a two input NAND, NOR and EXOR gates complete with a truth table and Boolean expression in each case. (3%) (b) State and prove De Morgan's laws for 3 input variable using truth tables. (5%) (c) State the principle of duality by means of the NAND gate Boolean expression: R = A. B (3%) (d) Draw the simplest logic circuit to perform the following function using NAND gates only: F = A C D.. + A B D.. + A C D.. ( 5 23 %) [ 16 23 %]
Q2. (a) Write a minimum sum of products expressions for the Karnaugh map of the logic switching operation in Fig. Q2. (4%)
(b) Minimise the Boolean expression: F = ABC + ACD + ABD + AC + BCD by means of (i) Boolean reduction and (ii) Karnaugh map. Which do you think is the easiest method to use? ( 8 23 %) (c) Draw the logic circuit of the minimized expression in part (b) of your answer. (4%) [ 16 23 %]
C ⋅ D C ⋅ D C ·D C ⋅ D
A ⋅ B A ⋅ B A·B A ⋅ B
Fig.Q
Q3. (a) Draw the logic circuit of a clocked SR flip flop using NAND gates. Examine the response of the flip flop via a truth table for the various input combinations and comment. What is the role of the clock input in such a circuit and point out any difficulties in circuit operation? ( 5 23 %) (b) Using the clocked SR flip flop in part (a) draw the logic circuit block diagram of a JK Flip Flop and complete its truth table. What operational feature does the JK flip flop have over that of the SR device? (6%) (c) Draw the block schematic of a 4 stage serial in parallel out shift register using D type flip flops. Examine the operation of the shift register using a state table for each stage in the loading of the binary number 1101. (5%) [ 16 23 %]
Q4. (a) List the parameters of an ideal operational amplifier and explain the concept of virtual ground using a simple circuit diagram (3%)
R 2
R 1
Vo
V (^2) Fig****. Q
(b) Show that the voltage gain for the circuit in Fig.Q4 is Avf = 1 + R 2 R 1. Explain how the circuit can be modified as a voltage follower. ( 6 23 %) (c) Explain how the circuit in Fig. Q4 can be modified, via a circuit diagram, to provide a
difference amplifier such that v o = RR^21 ( V 2 − V 1 )
where V 1 is the additional input to the inverting terminal. (7%) [ 16 23 %]
Q6. (a) Use Mesh analysis to find the current flowing in each resistor in the circuit in Fig Q6. [ 8^1 / 3 marks ]
30V 20V
FIGURE Q (b) Use Node analysis to verify the results in part (a). [ 8^1 / 3 marks ]
Q7. (a) Explain , briefly , the following terms :
- the RMS value of a sine wave voltage.
- the periodic time of a sine wave voltage.
- the frequency of a sine wave voltage. [ 1 2 / 3 marks ]
(b) For the circuit shown in Fig Q7 , find
- the impedance of the RLC circuit in complex form.
- the magnitude of the impedance.
- the RMS current.
- the angle between the current and the applied voltage.
- the resonant frequency of the RLC circuit. [ 15 marks ]
10Sin(100πt)
1H
5 μF
FIGURE Q
Q8. (a) A circuit of resistance 10Ω and inductance 76.4mH in series is connected to a 130V , 50Hz supply. Calculate the power factor. [ 6^2 / 3 marks ] (b) A 200-V, 50-Hz motor-pump set lifts 600 kg of water per minute through a height of 20m. If the overall efficiency of the set is 61.3%, and the current taken 20A, calculate
- the power factor of the motor
- the value of the parallel capacitance required to improve the power factor to unity. [ 10 marks ]
