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User Manual
5.2.3 TWI (two-wire interface) / I^ C 2
- 1.0 Introduction....................................................................................................................................
- 1.1 Project Goal........................................................................................................................................
- 2.0 Parts List.........................................................................................................................................
- 2.1 Standard TekBot Base
- 2.2 Motor Controller Board (H-bridge)
- 2.3 Atmel AVR 8-bit Microcontroller............................................................................................
- 2.4 Spartan 3 FPGA XC3S200
- 2.5 ADCC-3850 Micron Camera....................................................................................................
- 2.6 Camera Daughter Board
- 2.7 SEMC Pulsar Camera Module Connector..............................................................................
- 3.0 Assembly and Installation………………………………………………………………………...
- 3.1 Power off
- 3.2 Interfacing Camera
- 3.3 Interfacing FPGA
- 3.4 Interfacing AVR
- 4.0 Basic Operation
- 4.1 Getting Started
- 4.2 Using TST...................................................................................................................................
- 4.3 Shutting down
- 4.4 Micron Camera Interface……………………………………………………………………...
- 5.0 TST Component Information
- 5.1 Motor Controller Board (H-Bridge)
- 5.1.1 Introduction
- 5.1.2 Features……………………………………………………………………………………………….
- 5.1.3 Interface the H-Bridge..........................................................................................................
- 5.2 AVR Microcontroller
- 5.2.1 Introduction
- 5.2.2 AVR Pins...............................................................................................................................
- 5.2.3.1 Introduction………………………………………………………………………………………..
- 5.2.3.2 Data Transfer……………………………………………………………………………………...
- 5.2.3.3 Address Packet Format…………………………………………………………………………..
- 5.2.3.4 Data Packet Format………………………………………………………………………………
- 5.2.3.5 SCL and SDA Pins………………………………………………………………………………..
- 5.2.3.6 TWI Register Description………………………………………………………………………..
- 5.3 Spartan 3 FPGA
- 5.3.1 Introduction
- 5.3.2 Overall Architecture
- 5.3.3 VGA Block Diagram and port map.......................................................................................
- 5.4 Camera
- 5.5 Camera Daughter Board
- 5.6 Verilog code……………………………………………………………………………………
- 5.7 AVR Code
- 5.7.2 fpga 5.7.1 Main function Error! Bookmark not defined.
- 5.7.3 TWI…………………………………………………………………………………………………………
- 5.7.4 Button………………………………………………………………………………………………………
- 5.7.5 Uart…………………………………………………………………………………………………………
- 5.7.6 Camera…………………………………………………………………………………………………….
- 5.7.7 Without Reaquire…………………………………………………………………………………………
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5.8.8With Reaquire…………………………………………………………………………………………….. 5.8.9 Color………………………………………………………………………………………………………
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2.0 Parts List
2.1 Standard TekBot Base
Two servers, a charger board, battery packs, a metal plate, and a plexiglass board.
2.2 Motor Controller Board
The motor controller board used on the TekBot base allows for digital control of two separate motors of up to 8 volts at 300 mA.
2.3 Atmel AVR 8-bit Microcontroller
The Microcontroller provides 16 Million Instructions per Second (MIPS), 32K of SRAM, 38 Khz Modulated IR transceiver, RS232 Compatible Serial Port, accessible ports and pins.
2.4 Spartan 3 FPGA XC3S
Spartan 3 provides 200,000 system gates, 173 user-defined I/O signals, twelve 18x18bit embedded multipliers, and twelve 18 k-bit blocks RAM.
2.5 ADCC-3850 Micron Camera
This camera contains a single integrated circuit which contains an image sensor and an image processor. It uses a 2-wire serial port for programming and control.
2.6 Camera Daughter Board
This will provide 3.3V to the camera; it will interface the FPGA, the camera, and the AVR board. The camera board will be powered from the FPGA.
2.7 SEMC Pulsar Camera Module Connector
The Pulsar camera module was designed for debugging the ADCC-3850 Micron camera. We are using this board as a means to draw leads from the small camera mount to our prototype camera daughter board.
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3.0 Assembly and Installation
3.1 Power off
Make sure the FPGA is unplugged before adding any components. This precaution is necessary for ease of assembly and to help minimize the possibility of damage during installation.
3.2 Interfacing Camera With the FPGA
Connect the VGA CMOS Camera Module to the FPGA. The correct expansion port for the camera module is Expansion Connector B1. Insert the daughter board such that the camera and digital output of FPGA are facing upward.
3.3 Interfacing FPGA
Connect the Camera Board pins of MCLK and Data 0-7 to the FPGA. Connect 5V and GND from the FPGA to the AVR, Camera Board. Output 4 pins from the camera to the AVR for color recognition signals.
3.4 Interfacing the AVR to the Camera and FPGA
Connect the Camera Board Module to the AVR Microcontroller TWI pins at PORT D pin0 and pin1. Then connect Port D +5 and ground of the AVR board to port J2 of the camera board to provide power. Have the FPGA color recognition outputs connected to PORTA pin 2, 3, 4, 5.
User Manual
microprocessor. The large volume of data from the camera is reduced to various parameters which can be read. Image data can be sent out a VGA pot, but this is only in an 8 color space so the images are low quality. This VGA image is only intended for debugging and aiming. The image coordinate system has (0,0) at the upper left corner.
Camera Interface
This logic expects the camera to send 3 bytes per pixel containing either Red, Green and Blue (RGB), or Luminance and Chrominance signals (Technically Y, Cb, Cr, but sometimes referred to as YUV). It also expects an image 640 pixels wide and 480 lines high. The user may choose whether or not to run the camera with the automatic exposure and white balance function active. In many environments, it is best to allow these to operate initially, then disable them before selecting the target color range. If the illumination and the target are fixed, then it is usually best to set the exposure and white balance to predefined levels.
Registers
General Registers
0x00 – control This register sets the main operating mode and enables various features
Bit 7 6 5 4 3 2 1 0 cam_rst stat_en cur_en yuv mode Reset 0 0 0 0 0
Mode
Mode Name Description 0 idle Do nothing 1 display Display crude image from camera 2 calibrate Compute stats for cursor region 3 track Find target and display match data
Yuv The yuv bit tells the logic that the camera is outputting YCbCr data. Otherwise it expects RGB data. cur_en The cur_en bit enables display of the cursor. Use the cursor registers to set the location. stat_en The stat_en bit enables updating of the statistics register at the end of each frame, when in calibrate or track modes. cam_rst The cam_rst bit enables drives the camera's reset pin active (low).
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Target Definition Registers
0x10 – target_r_y_min The minimum red or Y value to match the target. Note the target matching logic simply compares the component values from the camera with these registers in the order they are output from the camera. It does not know the significance of the components (rgb, yuv, ...). 0x11 – target_r_y_max The maximum red or Y value to match the target. 0x12 – target_g_u_min The minimum green or Cb (U) value to match the target. 0x13 – target_g_u_max The maximum green or Cb (U) value to match the target. Micron Camera Interface Logic 2 Copyright © 2006 Micron Technologies 0x14 – target_b_v_min The minimum blue or Cr (V) value to match the target. 0x15 – target_b_v_max The maximum blue or Cr (V) value to match the target.
Target Boundary Registers
0x20 – bound_x_min_lo The lower byte of the minimum x coordinate of the pixels which matched the target. Read only! 0x21 – bound_x_min_hi The upper byte of the minimum x coordinate of the pixels which matched the target. Read only! 0x22 – bound_x_max_lo The lower byte of the maximum x coordinate of the pixels which matched the target. Read only! 0x23 – bound_x_max_hi The upper byte of the maximum x coordinate of the pixels which matched the target. Read only! 0x24 – bound_y_min_lo The lower byte of the minimum y coordinate of the pixels which matched the target. Read only! 0x25 – bound_y_min_hi The upper byte of the minimum y coordinate of the pixels which matched the target. Read only! 0x26 – bound_y_max_lo The lower byte of the maximum y coordinate of the pixels which matched the target. Read only! 0x27 – bound_y_max_hi The upper byte of the maximum y coordinate of the pixels which matched the target. Read only!
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The upper byte of the count of pixels. 0x50 – ssq_r_lo The lower byte of the sum of the squares of the red values. 0x51 – ssq_r_b Byte 1 (counting from 0) of the sum of the squares of the red values. 0x52 – ssq_r_b Byte 2 (counting from 0) of the sum of the squares of the red values. 0x53 – ssq_r_hi The upper byte of the sum of the squares of the red values. 0x50 – ssq_g_lo The lower byte of the sum of the squares of the green values. 0x51 – ssq_g_b Byte 1 (counting from 0) of the sum of the squares of the green values. Micron Camera Interface Logic 5 Copyright © 2006 Micron Technologies 0x52 – ssq_g_b Byte 2 (counting from 0) of the sum of the squares of the green values. 0x53 – ssq_g_hi The upper byte of the sum of the squares of the green values. 0x50 – ssq_b_lo The lower byte of the sum of the squares of the blue values. 0x51 – ssq_b_b Byte 1 (counting from 0) of the sum of the squares of the blue values. 0x52 – ssq_b_b Byte 2 (counting from 0) of the sum of the squares of the blue values. 0x53 – ssq_b_hi The upper byte of the sum of the squares of the blue values.
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5.0 TST Component Information
The objective of our design is to create a camera Tekbot that approaches a user defined target using the camera. At the heart of the design lies a Micron 1 Megabyte camera. The camera will stream video to a Xilinx Spartan III FPGA board, which will primarily distinguish a user-defined target and compute an X, Y coordinate located at the center of the target. This coordinate will then be relayed to the Atmega128 chip on the Tekbot, resulting in the Atmega128 sending the command to the Tekbot motors to drive towards the target. The Micron camera will allow the user to define a target based upon color.
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Port B pins 4, 5, 6, 7 are used to control the H-Bridge. Port B4 controls the enable of the right motor. Port B5 controls the direction of the right motor. Port B6 controls the enable of the left motor. Port B7 controls the direction of the left motor.
Port D pin 0 and 1 are used for TWI. Port D0 is the SCL and Port D1 is the SDATA. SCL will be an output from the AVR whereas SDATA serve as a bi- directional port outputting settings to the camera and receiving an acknowledgement. The main function of the TWI connection is to provide initial settings for the camera; this will be discussed about later in the documentation.
5.2.3 TWI (two-wire interface)
5.2.3.1 Introduction
For a brief overview of TWI/ , please refer to the camera section of the documentation. This section briefly overviews the application of TWI with the CRT (Camera Range-finder TekBot).
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The four things we control with TWI are:
- Frame rate: 8 FPS
- Size: 80 x 60 pixels
- Format: RGB 1 byte/pixel
- Clock: 12.5 MHz
The Atmel mega 128, the microprocessor on our AVR board, was perfect for TWI use because it could support both master and slave modes of operation, has a 7-bit address space which allows up to 128 different slave addresses, a fast transfer speed of 400 kHz, and something that was desperately needed, noise suppression circuitry. Another powerful tool was that we were able to run the AVR board on low power by running it on “sleep mode” and then when it recognizes an address, it will wake-up.
5.2.3.2 Data Transfer
TWI transfers data by sending information through the SDA bus and each bit of data transmitted is followed by a pulse from the SCL line. In the image below, it shows two levels of the SCL: data stable and data change. This must be the case in every situation except for start and stop modes.
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The start and stop condition, which is controlled by the master, determines when data is transmitted and terminated.
Looking at the diagram above, you can see that when SCL is high, changing the level of SDA will either make it a START or STOP condition. On the fourth change, you see a REPEATED START which is simply another START command while there was already a START command. This happens because the master does not wish to give up control of the data transmission. The REPEATED START acts exactly like a normal START but the difference is that it interrupts the previous START.
5.2.3.3 Address Packet Format
The format for data on a TWI bus is 9 bits long: 7 address bits, one READ/WRITE contrite and an acknowledge bit. When READ/WRITE is set, a read operation is performed. When a slave receives the address instruction, it responds by pulling the SDA buss low in the ninth SCL cycle (this is also called the acknowledge cycle). If the slave is busy, the SDA line is left high and then the master can transmit a STOP command or a START (implied REPEATED START) to try again or address another slave.
The order of data transmission is that the MSB of the address byte is first. 0000000 is reserved for a general call and when one is issued, all slaves respond by pulling the SDA line low during the ACK cycle. The reason for a general call is because the master wants to write the same information to multiple slaves; therefore, the general call is followed by a write bit.
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SLA+read/write, one or more data packets and a STOP condition. A START and STOP with nothing in between is not allowed. The way the master and slave communicate is through the wired-AND structure of the SCL line that was discussed earlier. If, for instance, the clock speed of the master is set too fast for the slave to handle, the slave can stall and hold the SCL low. This is especially useful because it will not interrupt the SCL high period. In short, the slave can indirectly control the transfer speed of the TWI by delaying the SCL duty cycle.
5.2.3.5 SCL and SDA Pins
These pins are used for interfacing the AVR TWI with the rest of the microcontroller. They also have internal pull-ups in the AVR pads which can be enabled by setting the PORT bits. The SCL frequency is generated using this equation:
Where TWBR is set to 12 and TWPS is set to 0. With these values in mind, we find that the SCL frequency is 400 kHz, which is the maximum frequency which TWI can reach.
5.2.3.6 TWI Register Description (From the Atmega128 datasheet)
TWI Bit Rate Register – TWBR
- Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See equation above for calculating bit rates.
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TWI Control Register – TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.
- Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. - Bit 6 – TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-Wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
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TWI Status Register – TWSR
- Bits 7...3 – TWS: TWI Status These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2- bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. - Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. - Bits 1...0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler.
To calculate bit rates, equation on page 16. The value of TWPS1...0 is used in the equation.
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TWI Data Register – TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR are undefined. In the case of lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
- Bits 7...0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus.
