Verilog HDL Tutorial: A Comprehensive Guide to Hardware Description Languages, Exams of Verilog and VHDL

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Tutorial on Verilog HDL

HDL

Hardware Description Languages

„

Widely used in logic design

„

Verilog and VHDL

Describe hardware using code

„

Document logic functions

„

Simulate logic before building

„

Synthesize code into gates and layout

„

Requires a library of standard cells

Why use Verilog HDL

„

Digital system are highly complex.

„

Verilog language provides the digital designera software platform.

„

Verilog allows user to express their designwith behavioral constructs.

„

A program tool can convert the Verilogprogram to a description that was used tomake chip, like VLSI.

Module ports

Module name

Verilog keywords

Taste of Verilog

module

Add_half ( sum, c_out, a, b );

input

a, b;

output

sum, c_out;

wire

c_out_bar;

xor

(sum, a, b);

//

xor

G1(sum, a, b);

nand

(c_out_bar, a, b);

not

(c_out, c_out_bar);

endmodule

Declaration of port Declarationmodes

DeclarationDeclaration of internalsignal

Instantiation of primitiveInstantiationgates

c_out

a b

sum

c_out_bar G1^ G

Lexical Convention

„

Numbers are specified in the traditional formor below.

„

Size: contains

decimal digitals that specify the

size of the constant in the number of bits.

„

Base format: is the single character

‘

followed

by one of the following charactersb(binary),d(decimal),o(octal),h(hex).

„

Number: legal digital.

Lexical Convention

„

Example :

347

// decimal number

4

’

b

//

4- bit binary number 0101

2

’

o

// 2-bit octal number

5

’

h87f

// 5-bit hex number h87f

2

’

d

// 2-bit decimal number

„

String in double quotes

“

this is a introduction

”

Program structure

„

Structure

module

(< port list>);

< declares> endmodule

. Module name

an identifier that uniquely names the module

.

. Port list

a list of input, inout and output ports which are

referenced in other modules.

Program structure

. Declares

section specifies data objects as registers,

memories and wires as well as procedural constructssuch as functions and tasks

.

. Module items

initial constructsalways constructsassignment ………………

.

Three Modeling Styles in Verilog

Structural modeling (Gate-level)

„

Use predefined or user-definedprimitive gates.

Dataflow modeling

„

Use assignment statements (

assign

)

Behavioral modeling

„

Use procedural assignmentstatements (

always

)

Structural model

//structural model of a NAND gate// program nand2.vmodule my_NAND(A, B, F);

input A, B;output F;nand G(F, A, B); // first parameter must be output. endmodule

//Gate-level description of a 2-to-4-line decoder//Figure 4-19 module decoder_gl (input A,B,E, output [0:3] D);

wire Anot, Bnot, Enot;not

n1 (Anot, A),n2 (Bnot, B),n3 (Enot, E); nand

n4 (D[0], Anot, Bnot, Enot),n5 (D[1], Anot,B, Enot),n6 (D[2], A, Bnot, Enot),n7 (D[3], A, B, Enot);

endmodule

Structural Modeling

//Gate-level hierarchical description of 4-bit adder// Description of half adder (see Fig 4-5b)//module halfadder (S,C,x,y);

// input x,y;// output S,C; module halfadder (output S,C, input x,y); //Instantiate primitive gates

xor (S,x,y);and (C,x,y); endmodule //Description of full adder (see Fig 4-8) module fulladder (output S,C, input x,y,z);

wire S1,C1,C2; //Outputs of first XOR and two AND gateshalfadder HA1 (S1,C1,x,y), HA2 (S,C2,S1,z);

//Instantiate the halfadder

or g1(C,C2,C1); endmodule

Dataflow Modeling

//HDL Example 4-3//----------------------------------------------//Dataflow description of a 2-to-4-line decoder//See Fig.4-19module decoder_df (output [0:3] D, input A, B,enable);

assign D[0] = ~(~A & ~B & ~ enable),D[1] = ~(~A & B & ~ enable),D[2] = ~(A & ~B & ~ enable),D[3] = ~(A & B & ~ enable);

endmodule

Dataflow Modeling

//HDL Example 4-4//----------------------------------------//Dataflow description of 4-bit addermodule binary_adder (A, B, Cin, SUM, Cout);

input [3:0] A,B;input Cin;output [3:0] SUM;output Cout;assign {Cout, SUM} = A + B + Cin; endmodule

concatenation

Binary addition