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An introduction to hardware description languages (hdls), focusing on verilog and vhdl. The role of hdls in digital design, their data types, syntax, and structure. It also covers the declaration of wires and registers, arrays, and constants. Although the document mentions the verilog program structure and a half-adder example, it is not meant for in-depth study at this time.
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Lecture 4 Appendix B Hardware Description Languages Study section B.5 page B-26 through B-31. Study and/or read section B.4 as directed in the following notes. Section B. Verilog and VHDL are the two most common HDLs. We will study Verilog in this course. We will not become experts, a beginning knowledge of Verilog is all that we want at this time. HDLs may be simulated or synthesized automatically. (Compiled)
Two primary data types : wire ## Specifies a combinational signal reg ## Holds a value—ie memory, or a cpu register or … Syntax: wire[31:0] ## Declares a wire that has 32 bits. reg[31:0] ## Declares a reg that has 32 bits. Arrays of registers: reg[31:0] R[0:31] ## Declares an array R of 32 bit reg. Then R[5] would refer to register number 5. Values (of bits): 0, or 1 ## usual meaning F,T, two valued logic z ## value unknown z ## tristate gate values—beyond this course.
Verilog Program Structure We will learn about the structure, slowly by example. Thus the following is read only (not study material) at this time. Other material to read at this time as opposed to studying.
Now we are back in the study mode, you are expected to comprehend the next figure in detail. It describes a half-adder that you have seen before in our notes or in Section B.5.
You should be able to read the above and interpret it in terms of the ALU design work we have done previously in our notes (section B.5). What is missing in this module? Carryout anyone?
