Virtual Memory - Operating Systems and Architecture - Lecture Slides, Slides of Computer Science

Download Virtual Memory - Operating Systems and Architecture - Lecture Slides and more Slides Computer Science in PDF only on Docsity!

1

Virtual Memory I

Chapter 8

2

Hardware and Control

Structures

• Memory references are dynamically translated into physical addresses at run time - A process may be swapped in and out of main memory such that it occupies different regions
• A process may be broken up into pieces that do not need to located contiguously in main memory
• All pieces of a process do not need to be loaded in main memory during execution

4

Execution of a Program

• Piece of process that contains the logical address is brought into main memory - Operating system issues a disk I/O Read request - Another process is dispatched to run while the disk I/O takes place - An interrupt is issued when disk I/O complete which causes the operating system to place the affected process in the Ready state

5

Advantages of

Breaking up a Process

• More processes may be maintained in main memory - Only load in some of the pieces of each process - With so many processes in main memory, it is very likely a process will be in the Ready state at any particular time
• A process may be larger than all of main memory

7

Thrashing

• Swapping out a piece of a process just before that piece is needed
• The processor spends most of its time swapping pieces rather than executing user instructions

8

Principle of Locality

• Program and data references within a process tend to cluster
• Only a few pieces of a process will be needed over a short period of time
• Possible to make intelligent guesses about which pieces will be needed in the future
• This suggests that virtual memory may work efficiently

10

Paging

• Each process has its own page table
• Each page table entry contains the frame number of the corresponding page in main memory
• A bit is needed to indicate whether the page is in main memory or not

11

Paging

13

14

Two-Level Scheme for

32-bit Address

16

Inverted Page Table

• Used on PowerPC, UltraSPARC, and IA-64 architecture
• Page number portion of a virtual address is mapped into a hash value
• Hash value points to inverted page table
• Fixed proportion of real memory is required for the tables regardless of the number of processes

17

Inverted Page Table

• Page number
• Process identifier
• Control bits
• Chain pointer

19

Translation Lookaside Buffer

• Each virtual memory reference can cause two physical memory accesses - One to fetch the page table - One to fetch the data
• To overcome this problem a high-speed cache is set up for page table entries - Called a Translation Lookaside Buffer (TLB)

20

Translation Lookaside Buffer

• Contains page table entries that have been most recently used