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VTU 3RD SEM CSE LOGIC DESIGN NOTES 10CS33, Study notes of Digital Logic Design and Programming

Visvesvaraya Technological UniversityDigital Logic Design and Programming

VTU 3RD SEM CSE LOGIC DESIGN NOTES 10CS33

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LOGIC DESIGN
(Common to CSE & ISE)
Subject Code: 10CS33 I.A. Marks : 25
Hours/Week : 04 Exam Hours: 03
Total Hours : 52 Exam Marks: 100
PART-A
UNIT – 1 7 Hours
Digital Principles, Digital Logic: Definitions for Digital Signals, Digital Waveforms, Digital Logic, 7400 TTL
Series, TTL Parameters The Basic Gates: NOT, OR, AND, Universal Logic Gates: NOR, NAND, Positive and
Negative Logic, Introduction to HDL.
UNIT – 2 6 Hours
Combinational Logic Circuits
Sum-of-Products Method, Truth Table to Karnaugh Map, Pairs Quads, and Octets, Karnaugh Simplifications,
Don’t-care Conditions, Product-of-sums Method, Product-of-sums simplifications, Simplification by Quine-
McClusky Method, Hazards and Hazard Covers, HDL Implementation Models.
UNIT – 3 6 Hours
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, Encoders, Exclusive-or Gates, Parity
Generators and Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL
Implementation of Data Processing Circuits
UNIT – 4 7 Hours
Clocks, Flip-Flops: Clock Waveforms, TTL Clock, Schmitt Trigger, Clocked D FLIP-FLOP, Edge-triggered D
FLIP-FLOP, Edge-triggered JK FLIP-FLOP, FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact
Bounce Circuits, Various Representation of FLIP-FLOPs, Analysis of Sequential Circuits, HDL Implementation of
FLIP-FLOP
PART-B
UNIT – 5 6 Hours
Registers: Types of Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In - Serial Out, Parallel In -
Parallel Out, Universal Shift Register, Applications of Shift Registers, Register Implementation in HDL
UNIT – 6 7 Hours
Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter Modulus,
Decade Counters, Presettable Counters, Counter Design as a Synthesis problem, A Digital Clock, Counter Design
using HDL
UNIT – 7 7 Hours
Design of Synchronous and Asynchronous Sequential Circuits: Design of Synchronous Sequential Circuit:
Model Selection, State Transition Diagram, State Synthesis Table, Design Equations and Circuit Diagram,
Implementation using Read Only Memory, Algorithmic State Machine, State Reduction Technique.
Asynchronous Sequential Circuit: Analysis of Asynchronous Sequential Circuit, Problems with Asynchronous
Sequential Circuits, Design of Asynchronous Sequential Circuit, FSM Implementation in HDL
UNIT – 8 6 Hours
D/A Conversion and A/D Conversion: Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A
Accuracy and Resolution, A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method, Continuous
A/D Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy and Resolution
Text Book:
1. Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 7th Edition,
Tata McGraw Hill, 2010.
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Download VTU 3RD SEM CSE LOGIC DESIGN NOTES 10CS33 and more Study notes Digital Logic Design and Programming in PDF only on Docsity!

(Common to CSE & ISE)

Subject Code: 10CS33 I.A. Marks : 25

Hours/Week : 04 Exam Hours: 03

Total Hours : 52 Exam Marks: 100

PART-A

UNIT – 1 7 Hours

Digital Principles, Digital Logic: Definitions for Digital Signals, Digital Waveforms, Digital Logic, 7400 TTL

Series, TTL Parameters The Basic Gates: NOT, OR, AND, Universal Logic Gates: NOR, NAND, Positive and

Negative Logic, Introduction to HDL.

UNIT – 2 6 Hours

Combinational Logic Circuits

Sum-of-Products Method, Truth Table to Karnaugh Map, Pairs Quads, and Octets, Karnaugh Simplifications,

Don’t-care Conditions, Product-of-sums Method, Product-of-sums simplifications, Simplification by Quine-

McClusky Method, Hazards and Hazard Covers, HDL Implementation Models.

UNIT – 3 6 Hours

Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, Encoders, Exclusive-or Gates, Parity

Generators and Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL

Implementation of Data Processing Circuits

UNIT – 4 7 Hours

Clocks, Flip-Flops: Clock Waveforms, TTL Clock, Schmitt Trigger, Clocked D FLIP-FLOP, Edge-triggered D

FLIP-FLOP, Edge-triggered JK FLIP-FLOP, FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact

Bounce Circuits, Various Representation of FLIP-FLOPs, Analysis of Sequential Circuits, HDL Implementation of

FLIP-FLOP

PART-B

UNIT – 5 6 Hours

Registers: Types of Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In - Serial Out, Parallel In -

Parallel Out, Universal Shift Register, Applications of Shift Registers, Register Implementation in HDL

UNIT – 6 7 Hours

Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter Modulus,

Decade Counters, Presettable Counters, Counter Design as a Synthesis problem, A Digital Clock, Counter Design

using HDL

UNIT – 7 7 Hours

Design of Synchronous and Asynchronous Sequential Circuits: Design of Synchronous Sequential Circuit:

Model Selection, State Transition Diagram, State Synthesis Table, Design Equations and Circuit Diagram,

Implementation using Read Only Memory, Algorithmic State Machine, State Reduction Technique.

Asynchronous Sequential Circuit: Analysis of Asynchronous Sequential Circuit, Problems with Asynchronous

Sequential Circuits, Design of Asynchronous Sequential Circuit, FSM Implementation in HDL

UNIT – 8 6 Hours

D/A Conversion and A/D Conversion: Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A

Accuracy and Resolution, A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method, Continuous

A/D Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy and Resolution

Text Book:

1. Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 7th^ Edition,

Tata McGraw Hill, 2010.

TABLE OF CONTENTS

  • UNIT 1: DIGITAL PRINCIPLES 1-
  • UNIT 2: COMBINATIONAL LOGIC CIRCUITS 12-
  • UNIT 3: DATA PROCESSING CIRCUITS 22-
  • UNIT 5: REGISTERS 37-
  • UNIT 6: COUNTERS 49-

VOLTAGE LEVELS

  • The output voltage level of any digital-circuit depends on its load (Figure: 1.4).
  • When Vo=HIGH, the voltage should be +5 V dc. In this case, the digital circuit must act as a current-source to deliver the current Io to the load (Figure 1.4a).
  • However, the circuit may not be capable of delivering necessary current Io while maintaining +5 V dc. To account for this, it is agreed that any output voltage close to +5 V dc within a certain range will be considered high.
  • When Vo= LOW, the voltage should be +0 V dc. In this case, the digital circuit must act as a current-sink. i.e. it must accept a current Io from the load and deliver it to ground (Figure 1.4b).

Figure 1.4: Loading of digital circuit

SWITCHING TIME

  • If the digital circuit were ideal, it would change from high to low (or from low to high), in zero time. Thus, the output voltage would never have a value in the forbidden range (Figure 1.5).
  • In reality, it requires a finite amount of time for Vo to make the transition between levels.
  • Vo may have a value within the forbidden region only during the short time while changing from high to low (or low to high). When not switching, Vo must either be in the high band or the low band.
  • The time required for voltage to make the transition from its high level to its low level is defined as fall time. The time required for voltage to make the transition from its low level to its high level is defined as rise time.
  • Fall time is measured between 0.9H and 1.1L. On the other hand, rise time is measured between 1.1L and 0.9H.

Figure 1.5: Switching in digital circuit

PERIOD & FREQUENCY

  • Period(T) is the time over which the signal repeats itself (Figure: 1.6).
  • Frequency (f) can be defined as f=1/T.

SYSTEM CLOCK

  • This is an oscillator circuit having a very precise frequency.
  • Frequency stability is provided by using a crystal as the frequency determining element.

Figure 1.6: (a)Symmetrical signal with period T (b)Asymmetrical signal with period T (c)System clock.

DUTY CYCLE

  • For a periodic digital signal, duty cycle is defined as

→ ratio of high level time to the period or

→ ratio of low level time to the period (Figure: 1.6).

i.e. Duty cycle H=tH/T Duty cycle L=tL/T

  • In other words, it is a convenient measure of how symmetrical or unsymmetrical a waveform is.

GENERATING LOGIC LEVELS

  • The digital voltage can be produced using a switch.
  • In figure 1.7a & 1.7b, when the switch is down, Vo=L=0=0V dc. When the switch is up, Vo=H=1=+5V dc.
  • Advantage: Switch is easy to use and easy to understand. Disadvantage: Switch must be operated by hand (i.e. manually).
  • A relay is a switch that is actuated by applying a voltage Vi to a coil (Figure: 1.7).
  • The coil current develops a magnetic field that moves the switch-arm from one contact to the other.
  • When Vi=0, Vo=L=0V dc. When Vi=+5V dc, Vo=H=+5V dc.
  • A digital integrated circuit(IC) is constructed using numerous transistors and resistors. Each IC is designed to perform a given logic operation. On an IC, each transistor is used as an electronic switch.

Figure 1.7: (a)Switch (b)Switch (c)Normally low relay

INVERTER

  • Negation operation requires a circuit that will invert a digital level. This logic circuit is called an inverter (Figure: 1.10).
  • When the input to this circuit is low, the switch remains up and the output is high. When the input is high, the switch moves down and the output is low.

Figure 1.10: Digital inverter (a)Model (b)Truth table (c)Symbol

TRI STATE INVERTER

  • When G=LOW, the inverter is connected to the output. i.e. when G=LOW, the circuit is activated and output Vo is the inverse of the input Vi (Fig: 1.11).
  • When G=HIGH, the enable switch opens, and the output is disconnected from the inverter.
  • Placing a circle at the input of a logic circuit means that circuit is activated when the signal at that input is low.

Figure 1.11: Inverting tri-state buffer (a)Model (b)Truth table (c)Symbol

AND GATE

  • This is a digital circuit having 2 or more inputs and a single output (Figure: 1.12 & 1.13).
  • The operation of an AND gate can be expressed as follows
    1. If any input is low, Vo will be low.
    2. Vo will be high only when all inputs are high.
    3. Vo=H only if V 1 =H, and V 2 =H and Vn=H.

Figure 1.12: AND gate

Figure 1.13: Two input AND gate (a)Model (b)Truth table (c)Symbol

OR GATE

  • It is a digital circuit having 2 or more inputs and a single output (Figure: 1.14& 1.15).
  • The operation of OR gate can be expressed as follows
    1. Vo will be low only when all inputs are low.
    2. If any input is high, Vo will be high.
    3. Vo =H if V 1 or V 2 or Vn=H

Figure 1.14: OR gate

Figure 1.15: Two input OR gate (a)Model (b)Truth table (c)Symbol

NAND GATE

  • This represents an AND gate followed by an inverter (Figure 2.25 & Table 2.3).

Figure 2.25: (a)Truth table (b)NAND symbol

XOR GATE

  • This produces output HIGH only when odd number of 1s is present at the input (Figure: 4.30).
  • This can be used as even parity bit generator.

Figure 4.30: (a)Truth table (b)XOR symbol

UNIVERSAL LOGIC GATES

  • Any logic function can be realized using only NAND gates or only NOR gates. For this reason, AND & NOR gates are called universal gates.
  • Realization of other gates using only NAND gates (Figure 2.21).

Figure 2.21: Universality of NOR gate (a)NOT from NOR (b)OR from NOR (c)AND from NOR

  • Realization of other gates using only NOR gates (Figure 2.27).

Figure 2.27: Universality of NAND gate (a)NOT from NAND (b)OR from NAND (c)AND from NAND

POSITIVE AND NEGATIVE LOGIC

  • We know that, in binary logic, two voltage levels represent the two binary digits, 1 and 0. Table 2.
  • In positive logic , the lower voltage level is assigned binary 0 & higher voltage level is assigned binary 1. So, we can convert table 2.8 to table 2.9. HIGH= LOW= Table 2.
  • In negative logic , the lower voltage level is assigned binary 1 & higher voltage level is assigned binary 0. So, we can convert table 2.8 to table 2.10. HIGH= LOW= Table 2.

Figure 2.35: meaning of symbol depends on whether you use positive or negative logic

Table 2.9: voltage definition for basic gates

ASSERTION LEVEL

  • To activate, if an input line has a bubble on it, you assert the input by making it low. If there is no bubble, you assert the input by making it high. This is called as Assertion level.

PREPARATION OF TEST BENCH

  • Here, we write a verilog code for simulating a OR gate
  • The test bench creates an input in the form of a timing waveform and passes this to OR gate module through a function or procedural call.
  • To generate timing waveform, we use time delay available in the form of #n where n=number in decimal that gives delay in nanoseconds.
  • Input values to a variable can be provided through syntax m'tn where m=number of digits, t=type of number and n=value to be provided.
  • The keyword 'reg' is used to hold value of a data object in a procedural assignment.
  • The keyword 'initial' ensures sequential execution of codes following it, but once.
  • The keyword 'always' is used for sequential execution but for infinite time.

module testor; //simulation module given a name tester reg A,B; //storage of data for passing it to module or_gate wire x; or_gate org(A,B,x); //circuit is instantiated with the name,or_gate initial //starts simulation begin // input is generated to test the circuit through following statements, simulation begins A=1'b0;B=1'b0; // 1'b0 signifies on binary digit with a value 0,AB is assigned 00 #20 //delay of 20ns A=1'b0;B=1'b1; //after 20ns AB= #20 //another delays of 20ns A=1'b1;B=1'b0;

A=1'b1;B=1'b1;

end endmodule

module or_gate(A,B,x); //OR gate used as a procedure in simulation input A,B; //defines 2 input port output X; //defines 1 output port or #(20) g1(x,A,B); //gate declaration with a gate delay of 20ns,output is effected after 20ns endmodule

EXERCISE:

  1. Compare Analog vs Digital. (4)
  2. With a neat diagram, explain switching in digital circuit. (6)
  3. Define duty cycle. (2)
  4. With a neat diagram, explain switch & relay. (6)
  5. With a neat diagram, explain buffer. (4)
  6. With a neat diagram, explain tri state buffer. (4)
  7. With a neat diagram, explain inverter. (4)
  8. With a neat diagram, explain tri state inverter. (4)
  9. With a neat diagram, two input AND gate. (4)
  10. With a neat diagram, two input OR gate. (4)
  11. With a neat diagram, two input OR gate. (4)
  12. Explain universal gates. (4)
  13. Compare positive logic vs negative logic. (4)
  14. What is HDL? What are its advantages? (2)
  15. Write verilog code for following circuits. (4)
  16. Explain preparation of test bench. (6)

UNIT 2: COMBINATIONAL LOGIC CIRCUITS

SUM OF PRODUCTS METHOD

  • The fundamental products are also called minterms (Figure: 3.3 & 3.4).
  • Product terms A'B, A'B, AB', AB are represented by mo, m1, m2 and m3 respectively.
  • For 'n' variable, there can be 2n^ number of minterms (Table: 3.1 & 3.2).

Table 3.1: Fundamental Products for two inputs

Figure 3.3: ANDing two variables and their complements

Table 3.2: Fundamental Products for Three inputs

Figure 3.4: ANDing three variables and their complements

Four-Variable Maps

  • Draw a kmap for logic equation Y=F(A,B,C,D)=€m(2,6,7,14)
  • Figure 3.9 shows four-variable kmap (Table 3.7).

Table 3.

Figure 3.9: Four variable kmap

PAIRS, QUADS AND OCTETS

  • A pair is a group of two 1s that are horizontally or vertically adjacent. It eliminates one variable and its complement (Figure: 3.12).
  • A quad is a group of four 1s that are horizontally or vertically adjacent. It eliminates 2 variables and their complements (Figure: 3.13).
  • Octet is a group of eight 1s. It eliminates three variables and their complements (Figure: 3.14).

Figure 3.12: Example of pairs

Figure 3.13: Example of quads

Figure 3.14: Example of octet

KMAP METHOD FOR SIMPLIFYING BOOLEAN EQUATIONS

  1. Enter a 1 on map for each fundamental product that produces a 1 output in truth table. Enter 0s elsewhere.
  2. Encircle the octets, quads and pairs.
  3. If any isolated 1s remain, encircle each.
  4. Eliminate any redundant group.
  5. Write boolean equation by ORing the products corresponding to the encircled group.

ENTERED VARIABLE MAP (EVM)

  • In this, one of the input variables is placed inside kmap. This is done separately noting how it is related with output.
  • This reduces the kmap size by 1 degree.
  • This technique is particularly useful for mapping problems with more than 4 input variables.
  • Entered variable map for Table: 3.6 is constructed as follows.

→ For AB=00, we find Y=0 and is not dependent on C (Figure: 3.10).

→ For AB=01, we find Y is complement of C thus we can write Y=C'

→ Similarly, for AB=10, Y=0 and for AB=11, Y=1.

Table 3.

Figure 3.10: Entered variable map

PRODUCT OF SUMS METHOD

  • Given a truth table, you identify the fundamental sums needed for a logic design.
  • Then by ANDing these sums, you get the product-of-sums equation corresponding to the truth table.
  • The fundamental sum produces an output 0 for the corresponding input condition.

CONVERTING A TRUTH TABLE TO AN EQUATION

  • Consider Table 3.9 and you want to get the product-of-sums equation.
  • We locate each output 0 in the truth table and write down its fundamental sum.
  • In Table 3.9, the first output 0 appears for A=0, B=0 and C=0. The fundamental sum for these inputs is A+B+C. Because this produces an output 0 for the corresponding input condition: Y=A+B+C=0+0+0=
  • Table 3.9 shows all the fundamental sums needed to implement the truth table.
  • Each variable is complemented when the corresponding input variable is a 1; the variable is uncomplemented when the corresponding input variable is 0.To get the product-of-sums equation, you have to AND the fundamental sums: Y=(A+B+C)(A+B'+C')(A'+B'+C)= M(0,3,6)
  • In POS, each sum term is called maxterm and is designated by Mi.

Table 3.9: Fundamental Sums for Three inputs

STEPS TO CONVERT BETWEEN STANDARD SOP & POS FORM

  1. Identify complementary locations
  2. Changing minterm to maxterm or reverse
  3. Changing summation by product or reverse.
  • This is known are conversion between canonical forms.

LIMITATIONS OF KMAP

  • The map method depends on the user's ability to identify patterns that gives largest size.
  • The map method becomes difficult to adapt for simplification of 5 or more variables.

SIMPLIFICATION BY QUINE MCCLUSKY METHOD

  • Quine McClusky method is a systematic approach for logic simplification that does not have the limitations of Kmap and also can easily be implemented in a digital computer.
  • Quine McClusky method involves preparation of 2 tables:

→ one determines prime implicants and

→ other selects essential prince implicants to get minimal expression.

  • Prince implicants are expressions with least number of literals that represents all the terms given in a truth table.
  • Prime implicants are examined to get essential prime implicants for a particular expression that avoids any type of duplication.

PROCEDURE USED FOR DETERMINING ESSENTIAL PRIME IMPLICANTS

  • Consider a 4-variable simplification problem for Table 3.10. Figure 3.32 shows prime implicant determination table for the problem.
  • In stage 1 of the process, we find out all the terms that gives output 1 from truth table (Table 3.10) and put them in different groups depending on how many 1 input variable combinations have. For example, first group has no 1 in input combination, second group has only one 1,third two 1s,fourth three 1s and fifth four 1s. We also write decimal equivalent of each combination to their right for convenience.
  • In stage 2, we first try to combine first and second group of stage 1,on a member to member basis.
  • The rule is to see if only one binary digit is differing between two members and we mark that position by '-'. This means corresponding variable is not required to represent those members.
  • In stage 3, we combine members of different groups of stage 2 in a similar way. Now it will have two '-' elements in each combination. This means each combination requires 2 literals to represent it.
  • There is no stage 4 for this problem. This completes the process of determination of prime implicants.

Table 3.

Figure 3.32: Determination of prime implicants