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Objectives
- Describe the Intel family of microprocessors.
- Explain the function of the Execution Unit and BIU.
- Describe pipelining and how it enables the CPU to work faster.
- Explain the list of registers of 8086 and this operation.
Introduction Webster's New Twentieth Century Dictionary defines microprocessor as "the controlling unit of a microprocessor, laid out on a tiny chip and containing the logical elements for handling data, performing calculations, carrying out stored instructions, etc."
Intel has brought out a series of microprocessors. The characteristic of each starting from 4-bit microprocessor to 64 bits microprocessor is listed below. For each processor note the number of transistors used, the clock speed, number of bits as well as the pin package has been indicated. There are many other features which will be discussed in detail as we go through the course.
Intel brought out the first 4 bit processor (1971)
- 2300 transistors
- 400 – 800 kHz
- 4-bit word size
- 16-pin DIP package
8-bit processor (1974-1976) 8085 Microprocessor
- 4.5k – 6.5k transistors
- NMOS Technology
- 5-10 MHz
- 8-bit word size
- 40-pin DIP package
- No. of instructions 111/
- 64K memory
- Address lines 16
- Data lines 8
- Microcode ROM
16-bit processor (1978-1979) 8086/8088 Microprocessor
- 3 μm process
- NMOS Technology
- 29k transistors
- 5-10 MHz
- 133 Instructions
- 16-bit word size
- 40-pin DIP package
- 1 M Bytes Physical Memory
- Microcode ROM
8-bit layout
16-bit layout
Difference between 8085 and 8086
No Description 8085 8086
1 Address lines 16 20
2 Memory 64K 1MB
3 Data Bus 8 16
4 Co-processor - 8087
5 Operating system CP/M DOS
CP / M , originally standing for Control Program/Monitor and later Control Program for Microcomputers, is a mass-market operating system created for Intel 8080/85-based microcomputers by Gary Kildall of Digital Research, Inc.
Difference between 8086 and 8088 Processor
No Description 8088 8086
1 Address lines 20 20
2 Memory 1MB 1MB
3 Data Bus 8 16
4 Co-processor 8087 8087
5 Operating system DOS OS/
80286 Microprocessor Virtual memory (1982) 1.5 μm process
- NMOS Technology
- 134k transistors
- 10-16 MHz
- 16-bit word size
- 16M Physical Memory
- 68-pin PGA(pin grid array)
- Bit-slices clearly visible Difference between 8086 and 80286
No Description 8086 80286
1 Address lines 20 24
2 No. of Pins 40 68
3 Virtual Memory Nil 1G
- Dynamic execution (1995-99)
- 3 micro-ops / cycle
- Out of order execution
- 16-32 KB Cache I$ & D$
- Multimedia instructions
- PIII adds 256+ KB L2$ Cache Pentium 4 Deep pipeline (2001) Very fast clock 256-1024 KB L2$ Characteristics 180 – 90 nm process 42-125M transistors 1.4-3.4 GHz 32-bit word size 478-pin PGA Units start to become invisible on this scale
8086 Microprocessor The Intel 8086 p is a 16-bit microprocessor intended to be used as a CPU in a microcomputer. The term "16-bits" means that its arithmetic logic unit, internal registers, and most of its instructions are designed to work with 16-bit binary words. The 8086 have a 16-bit data bus, so that it can read data from or write data to memory and ports (16-bits or 8-bits at a time).
The 8086 contain approximately 29000 transistors and is fabricated using the HMOS technology. The 8086 can be operated at 3 different clock speeds. The standard 8086 runs at 5Mhz and the other versions of the 8086, the 8086-2 and 8086 -1 permit a clock frequencies of up to 8Mhz and 10Mhz respectively.
8086/8088 - CPU Architecture The 8086/8088 architecture can be broadly divided into two groups: (i) Execution Unit (EU) (ii) Bus Interface Unit (BIU) The execution unit contains the Data and Address registers, the Arithmetic and Logic Unit and the Control Unit. The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory addressing logic and a Six byte instruction object code queue (4-byte instruction object-code queue in case of 8088 microprocessor). The execution unit and the Bus Interface unit operate asynchronously. The EU waits for the instruction object code to be fetched from the memory by the BIU. The BIU fetches or pre-fetches the object code (16-bits at a time) and loads it into the six bytes queue. Whenever the EU is ready to execute a new instruction, it fetches the instruction object code from the front of the instruction queue and executes the instruction in specified number of clock periods. If memory or Input/output devices must be accessed in the course of executing an instruction, then the EU informs the BIU of its needs. The BIU completes its operation code (opcode) fetch cycle, if in progress, and executes an appropriate external access machine cycle in response to the EU demand.
ES CS SS
Bus Interface Unit
Instructionqueue
ControlUnit Controllines General Registers
ALU
Flags
Execution Unit
AH(8) AL(8) BH(8) BL(8) CH(8) CL(8) DH(8) DL(8)
AX BX CX DX SP BP DI SI
DS IP
20 Adder
Fig 1.3 8086 Architecture
The BIU is independent of the EU and attempts to keep the six-byte queue filled with instruction object codes. If two or more of these six bytes are empty, then the BIU executes instruction fetch machine cycles as long as the EU does not have an active request for the bus access pending. If the EU issues a request for the bus access while the BIU is in the middle of an instruction fetch machine cycle, then the BIU will complete the instruction fetch machine cycle before honoring the EU bus access request. The EU does not use machine cycles; it executes instructions in some number of clock periods that are not subjected to any type of machine cycles. The only time clock periods are grouped is clock when the bus control logic wishes to access memory or I/O devices.
Execution Unit (EU) The execution unit consists of (i) General Registers (ii) Arithmetic Logic Unit (iii) Control unit (iv) Flag Registers
General Registers The CPU has eight 16-bit general registers. They are divided into two files of four registers each. They are: (a) The data register file and (b) The pointer and index register file AX BX CX DX
AH AL BH BL CH CL DH DL Fig. 1.4 Data Register File AX, BX, CX and DX registers are the data registers. The upper and lower halves of the data registers are individually addressable. AX register can be addressed as AL and AH registers, BX register can be addressed as BL and BH register, CX register can be addressed as CL and CH register, DX register can be addressed as DL and DH.
(i) Addition (ii) Subtraction (iii) Multiplication (iv) Division
Arithmetic operations may be performed on four types of numbers Unsigned binary numbers Signed binary numbers (Integers) Unsigned packed decimal numbers Unsigned unpacked decimal numbers
The ALU can also perform logical operations such as (i) NOT (ii) AND (iii) OR (iv) EXCLUSIVE OR (v) TEST Flag Register The Execution Unit has a 16-bit flag register which indicates some conditions affected by the execution of an instruction. Some bits of the flag register control certain operations of the EU. The flag register in the EU contains nine active flags shown in fig.1.6 D15 D14 D13 D12 D11 D10 D9 D8 D7 D D5 D4 D3 D2 D1 D
Fig, 1.6 Flag Register
Six of the nine flags are used to indicate some condition produced by an instruction. These condition flags are also called status flags of 8086/8088 microprocessor. These are the Carry flag, Parity flag, Auxiliary carry flag, Zero flag, and Sign flag. The other three Control flags are Trap Flag, Direction Flag and Interrupt flag.
Condition Flags
Carry Flag (CF)
This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of the most significant bit position or if there is a borrow to the MSB after subtraction. This flag is also affected when other arithmetic and logical instruction are executed.
Parity Flag (PF)
This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the result). This flag can be used to check for data transmission error.
Auxiliary Carry Flag (AF)
\This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibble to the lower. The auxiliary carry flag is used for decimal adjust operation. The AF flag is of significance only for byte operations duringwhich the lower order byte of the 16-bit word is used.
O D I T S Z AF PF CF
Zero Flag (Z) This flag is set when the result of an operation is zero. The flag is reset when theresult is not zero. Overflow Flag (O) This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result exceeded the storage capacity of the destination, and a significant digithas been lost. Sign flag (S) This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this flag is set the data in assumed to be negative and when this flag iszero it is assumed to be positive.
Control Flags Control flags are used to control certain operations of the processor. The application of these flags are different from that of six conditional flags. The conditional flags are set or reset by the EU on the basis of the result of some arithmetic or logic operations. The control flags are deliberately set or reset with specific instructions included in the program.
Trap flag (T) This is used for single stepping through a program. It is used for debugging theprograms. (Discusses with interrupts).
Interrupt Flag (I) It is used to allow / prohibit the interruption of a program. When the flag set, it enables the interrupt from INTR. When the flag is reset (0), it disables the interrupt.
Direction Flag (D) It is used for string instructiion (Discussed with the specific instructions later inthe book). If the direction flag is set, the pointers are decremented else the pointers areincremented.
Bus Interface Unit (BIU) The BIU sends out addresses, fetches instructions from memory, reads data from memory and ports, and writes data to ports and memory. In other words the BIU handlesall transfers of data and addresses on the buses for the execution unit. The BIU has
- An instruction queue
- An Instruction pointer
- Segment registers
Instruction Queue To speed up program execution, the BIU fetches as many as 6 insturction bytes ahead of time from memory. The prefetched instruction bytes are held for the EU in a first-in-first-out group of register called a queue. The EU decodes an instruction or executes an instruction which does not require the buses. When the EU is ready for its next instruction, it simply reads the instruction from the queue in the BIU. Fetching thenext instruction while the current instruction executes, is called pipelining. Note: The 8088 microprocessor has only a 4-byte queue.
Instruction Pointer (IP)
The Instruction Pointer is a 16-bit register. This register is always used as the effective memory address, and is added to the Code segment with a displacement of four bits to obtain the physical address of the opcode. The code segment cannot be changed by the move instruction. The instruction pointer is incremented after each opcode fetchto point to the next instruction.
0 10000h 20000h 30000h
Segment A Segment B
Segment C
Segment D
Segment E
Contiguous memory Fully overlap
Disjoint
Partial overlaped
Fig 1. FFFFFH A B C D E F G
H I
J 00000H
CS
DS
SS
ES
Fig-1.
Fig 1.8 shows the segment registers pointing to the various memory segments. Since logical addresses are 16-bits wide, up to 64K (65536) bytes in a given segment can be addressed.Each time the CPU need to generate a memory address, one of the segment registers is automatically chosen and its contents added to a logical address. For an instruction fetch, the code segment register is automatically added to the logical address (in this case, the contents of the instruction pointer) to compute the value of the instruction address. For stack referencing the stack segment register is automatically added to the logical address (the SP or BP register contents) to compute the value of the stack address.
For data reference operations, where either the data or extra segment register is chosen as the base, the logical address can be made up of many different types of values: it can be simply the immediate data value contained in the instruction, or it can be the sum of an immediate data value and a base register, plus an index register. Generally, the selection of the DS or ES register is made automatically, though provisions do exist to override this selection. Thus any memory location may be addressed without changing the value of the segment base register. In systems that use 64K or fewer bytes of memory for each memory area (code, stack, data and extra), the segment registers can be initialized to zero at the beginning of the program and then ignored, since zero plus a 16-bit offset yields a 16-bit address. In a system where the total amount of memory is 64K bytes or less, it is possible to set all segments equal and have fully overlapping segments.
Segment registers are also very useful for large programming tasks, which require isolation of program code from the data area, or isolation of module data from the stack information etc.
Segmentation makes it easy to build re-locatable and reentrant programs. In many cases, the task of relocating a program (relocation means having the ability to run the same program in several different areas of memory without changing addresses in the program itself) simply requires moving the program code and then adjusting the code segment register to point to the base of the new code area. Since programs can be written for the 8086 / 8088 in which all branches and jumps are relative to the instruction pointer, it does not matter what value is kept in the code segment register. Every application will define and use segments differently. The currently addressable segment override provide, a generous workspace: 64K bytes for code, 64K bytes stack and 128K bytes of data storage.
The Intel-8086, high performance 16-bit CPU is available in three clock speeds: 5, 8 and 10 MHz. The CPU is implemented in N-channel, depletion load, silicon gate technology (HMOS), and packaged in a 40 pin DIP package: The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels.
Pin Configuration Fig. 1.9 shows the pin configuration.
AD
40 Vcc 39 38 A16/S 37 A17/S 36 A18/S 35 A19/S 34 BHE/S MN/MX RD RG GT0/ (HOLD) RQ GT1/ (HLDA) LOCK WR( ) S2 (M/I0 ) S1 (DT/R ) S0 (DEN ) QS0 (ALE) QS1 ( INTA) TEST READY RESET
33 32 31 30 29 28 27 26 25 24 23 22 20 21
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
GND 1 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD NMI INTR CLK GND Fig. 1.9 Pin Configuration
The following pin function descriptions are for the microprocessor 8086 in either minimum or maximum mode. The 8086 pins signals are TTL compatible.
AD0 - AD15 (I/O): Address Data Bus These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) and data
during T2, T3 and T4 clock cycles. A0 is analogous to BHEfor the lower byte of the data bus, pins D0-
D7. A0 bit is Low during T1 state when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. These lines are active high and float to tri-state during interrupt acknowledge and local bus "Hold acknowledge". Fig. 1.10 shows the timing of AD 0 – AD 15 lines to access data and address.
AD0 - AD15 Address Data
T4 T1 T2 T3 T
to via an interrupt vector look up table located in system memory. It can be internally masked by software resetting the interrupt enable bitINTR is internally synchronized. This signal is active HIGH.
NMI (I): Non-Maskable Interrupt An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector look up table located in system memory. NMI is not maskable internallyby software. A transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current instruction. This input is internally synchronized.
Reset (I) Reset causes the processor to immediately terminate its present activity. To be recognised, the signal must be active high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to 8086 can be generated by the
- (Clock generation chip). To guarantee reset from power-up, the reset input must remain below 1. volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V. The RES input of the 8284 can be driven by a simple RC circuit as shown in fig.1.10.
+5V
R
Normal Reset Key
RES
F/C
X X2 CLK^ CLK
RESET RESET
SYSTEM RESET
8086 p
C
Fig. 1.
The value of R and C can be selected as follows: Vc (t) = V (1 - e -t /RC) t = 50 Micro sec. V = 4.5 volts, Vc = 1.05V and RC = 188 Micro sec. C = 0.1 Micro F; R = 1.88 K ohms.
CPU component Contents Flags Cleared Instruction Pointer 0000H CS register FFFFH DS register 0000H SS register 0000H ES register 0000H Queue Empty Table – 1.3 System Registers after Reset
8086/88 RESET line provide an orderly way to start an executing system. When the processor detects the positive-going edge of a pulse on RESET, it terminates all activities until the signal goes low, at which time it initializes the system as shown in table 1.
Ready (I) Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.
CLK (I): Clock
Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33% duty cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since the design of
ALE (O): Address Latch Enable ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated.
DT/ R (O): DATA Transmit/Receive
In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the direction
of data flow through the transceiver. This signal floats to tri-state off during local bus "hold acknowledge".
DEN (O): Data Enable
It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver.
DEN is active LOW during each memory and IO access. It will be low beginning with T2 until the
middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. It floats to tri-state off during local bus "hold acknowledge".
HOLD & HLDA (I/O): Hold and Hold Acknowledge
Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD must be active HIGH. The processor receiving the "HOLD" request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as being Low, the processor will lower the HLDA and when the processor needs to run another cycle, it will again drive the local bus and control lines.
Maximum Mode
The following pins function descriptions are for the 8086/8088 systems in maximum mode ( i.e.. MN/
MX = 0). Only the pins which are unique to maximum mode are described below.
S2, S1, S0 (O): Status Pins
These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the beginning of a bus cycle. These status lines are encoded as shown in table 1.4.
S2 S1 S0 Characteristics 0 0 0 Interrupt acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive State Table 1.
QS0, QS1 (O): Queue – Status Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS provide status to allow external tracking of the internal 8086instruction queue. The condition of queue status is shown in table 1. Queue status allows external devices like In-circuit Emulators or special instruction set extension co- processors to track the CPU instruction execution. Since instructions are executed from the 8086 internal queue, the queue status is presented each CPU clock cycle and is not related to the bus cycle activity. This mechanism allows
(1) A processor to detect execution of a ESCAPE instruction which directs the co-processor to perform a specific task and (2) An in-circuit Emulator to trap execution of a specific memory location.
QS1 QS1 Characteristics 0 0 No operation 0 1 First byte of opcode from queue 1 0 Empty the queue 1 1 Subsequent byte from queue Table 1.
LOCK (O)
It indicates to another system bus master, not to gain control of the system bus while LOCKis active
Low. The LOCKsignal is activated by the "LOCK" prefix instruction and remains active until the
completion of the instruction. This signal is activeLow and floats to tri-state OFF during 'hold acknowledge". Example:
LOCK XCHG reg., Memory ; Register is any register and memory GT 0
; is the address of the semaphore.
RQ / GT 0 and RQ / GT 1 (I/O): Request/Grant
These pins are used by other processors in a multiprocessor organization. Local bus
masters of other processors force the processor to release the local bus at the end of the
processors current bus cycle. Each pin is bi-directional and has an internal pull
upresistors. Hence they may be left un-connected.
Comparison of 8086 with the 8088 Microprocessor
The 8088 CPU is an 8-bit processor designed around the 8086 internal structure. Most internal functions of the 8088 are identical to the equivalent 8086 functions. The 8088 handles the external bus
the same way the 8086 does, one difference being that the 8088 handles only 8-bits at a time. 16-bit operands are fetched or written in two consecutive bus cycles. To an assembly language programmer both processors will appear identical with the exception of execution times. The internal register
structure is identical and all instructions produce the same end result. The pin configuration of 8088 is illustrated in fig. 1.14.
BHEhas no meaning on the 8088 and has been eliminated.
IO/ Mhas been inverted. i.e., (In 8086, this pin as IO/M)
ALE is delayed by one clock cycle in the minimum mode when entering HALT to allow the status to be latched with ALE.
Questions
- Compare 8086 and 8088 microprocessors. In what ways are they similar? In what ways do they differ?
- What is the purpose of the ALE signal in an 8086 system?
- What is the major difference between an 8086 operating in minimum mode and an 8086 operating in maximum mode?
- Describe the response of an 8086 when its RESET input is asserted high.
- Why are buffers often needed on the address, data and control buses in a microprocessor system?
6. What are the function of the 8086 DT/ Rand DENsignals?
- Explain the difference between a memory read cycle and an I/O read cycle.
- What does the ASYNC input to the 8284 accomplish?
- What logic levels must be applied to AEN1 and RDY1 to obtain a logic 1 at the ready pin?
- Explain the operation of the LOCK pin.
- What conditions do the QS1 and QS0 pins indicate about the 8086/8088?
- Explain the operation of the TEST pin and the WAIT instruction.
- What is the function of QS0 and QS1 signals?
Objective Questions
- State true or false (a) Both the address and data bus are unidirectional. (b) Both the 8086 and 8088 microprocessors address 64 K bytes of memory. (c) No difference exits between the memory maps of 8086 and 8088. (d) The string source (SI) is located in the Data Segment (DS) and the string destination is located in the Extra segment (ES) for string instructions.
- The INTR input is -- sensitive.
- The 8286 microprocessor has a 1-bit data bus. Its memory is organized into -- banks, each--bit wide.
- A microprocessor with a 24-bit address bus could access --- MB of memory.
- A bus cycle is equal to clocking --- periods.
- If the ready pin is grounded, it will introduce ---state into the bus cycle.
- The PCLK output of the 8284A is --- MHz if the crystal frequency is 14 MHz.
- The RES input to the 8284A is placed at a logic --- level in order to reset the
8086/8088.
- The 8086 and 8088 processor can be operated in either the minimum or maximummode. The maximummode is so named because the maximum mode
(a) Let you execute the maximum number of instructions. (b) Let you address the maximum number of memory locations (IMB) (c) Requires more support hardware than the minimum mode. (d) All of the above.
- The 8086/8088 use a multiplexed address and data bus because
(a) 40 pins is a good size for the IC. (b) Multiplexing is supported by 8085 Microprocessor. (c) Multiplexing reduces the number of lines between the microprocessor and the auxiliary Ics. (d) All of the above.
- The DEN signal is active ------- output from 8288 bus controller.
- An 8086/8088 microprocessor requires -------- and ------- chips is maximum mode systems configuration.
13.The 8288 bus controller must be used in the ------ mode to provide ------ signals to the memory and I/O.
- 8088 microprocessor does not required latch for a A8 – A15 lines because ---------.
- SSO of 8088 microprocessor indicates -------.
