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microprocessors
Typology: Study notes
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M. Krishna Kumar
MM/M3/LU9a/V1/
Compatible with All Intel and Most other Microprocessors
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Handles Inputs from DC to 10 MHz
8 MHz 825410 MHz 8254-
Status Read-Back Command
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Six Programmable Counter Modes
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Three Independent 16-Bit Counters
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Binary or BCD Counting
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Single a 5V Supply
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Standard Temperature Range
M. Krishna Kumar
MM/M3/LU9a/V1/
The Intel 8254 is a counter/timer device designed to solvethe common timing control problems in microcomputersystem design.
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It provides three independent 16-bit counters, each capableof handling clock inputs up to 10 MHz.
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All modes are software programmable. The 8254 is asuperset of the 8253.
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The 8254 uses HMOS technology and comes in a 24-pinplastic or CERDIP package.
M. Krishna Kumar
MM/M3/LU9a/V1/
Figure 2. 8254 Block Diagram
M. Krishna Kumar
MM/M3/LU9a/V1/
Symbol
PinNo.
Type
Name and Function
D7-D
1 - 8
I/O
DATA: Bi-directional three state data buslines, connected to system data bus.
CLK 0
9
I^
CLOCK 0: Clock input of Counter 0.
OUT 0
10
O
OUTPUT 0: Output of Counter 0.
GATE 0
11
I^
GATE 0: Gate input of Counter 0.
GND
12
GROUND: Power supply connection.
VCC
24
POWER: A 5V power supply connection.
WR
23
I^
WRITE CONTROL: This input is low duringCPU write operations.
RD
22
I^
READ CONTROL: This input is low duringCPU read operations.
M. Krishna Kumar
MM/M3/LU9a/V1/
GATE 2
16
I^
GATE 2: Gate input of Counter 2.
CLK 1
15
I^
CLOCK 1: Clock input of Counter 1.
GATE 1
14
I^
GATE 1: Gate input of Counter 1.
OUT 1
OUT 1
O
OUT 1: Output of Counter 1.
M. Krishna Kumar
MM/M3/LU9a/V1/
The 8254 is a programmable interval timer/counterdesigned for use with Intel microcomputer systems.
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It is a general purpose, multi-timing element that can betreated as an array of I/O ports in the system software.
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The 8254 solves one of the most common problems in anymicrocomputer system, the generation of accurate timedelays under software control. Instead of setting up timingloops in software, the programmer configures the 8254 tomatch his requirements and programs one of the countersfor the desired delay.
M. Krishna Kumar
MM/M3/LU9a/V1/
Programmable rate generator
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Square wave generator
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Binary rate multiplier
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Complex waveform generator
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Complex motor controller
M. Krishna Kumar
MM/M3/LU9a/V1/
: This 3-state, bi-directional, 8-bit
buffer is used to interface the 8254 to the system bus, seethe figure below : Block Diagram Showing Data BusBuffer and Read/Write Logic Functions.
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: The Read/Write Logic accepts
inputs from the system bus and generates control signalsfor the other functional blocks of the 8254. A
1
and A
0
select one of the three counters or the Control WordRegister to be read from/written into.
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A “low” on the RD input tells the 8254 that the CPU isreading one of the counters.
M. Krishna Kumar
MM/M3/LU9a/V1/
A “low” on the WR input tells the 8254 that the CPU iswriting either a Control Word or an initial count. Both RDand WR are qualified by CS; RD and WR are ignoredunless the 8254 has been selected by holding CS low.
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The Control Word
Register (see Figure 4) is selected by the Read/Write Logicwhen A
= 11. If the CPU then does a write operation to 0
the 8254, the data is stored in the Control Word Registerand is interpreted as a Control Word used to define theoperation of the Counters.
M. Krishna Kumar
MM/M3/LU9a/V1/
Figure 4. Block Diagram Showing Control Word Register and Counter Functions
M. Krishna Kumar
MM/M3/LU9a/V1/
The status register, shown in Figure 5, when latched,contains the current contents of the Control Word Registerand status of the output and null count flag. (See detailedexplanation of the Read-Back command.)
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The actual counter is labelled CE (for CountingElement''). It is a 16-bit presettable synchronous downcounter. OLM and OLL are two 8-bit latches. OL standsforOutput Latch''; the subscripts M and L stand forMost significant byte'' andLeast significant byte'‘respectively.
M. Krishna Kumar
MM/M3/LU9a/V1/
Figure 5. Internal Block Diagram of a Counter
M. Krishna Kumar
MM/M3/LU9a/V1/
Similarly, there are two 8-bit registers called CRM andCRL (for ``Count Register''). Both are normally referred toas one unit and called just CR.
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When a new count is written to the Counter, the count isstored in the CR and later transferred to the CE. TheControl Logic allows one register at a time to be loadedfrom the internal bus. Both bytes are transferred to the CEsimultaneously.
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CRM and CRL are cleared when the Counter isprogrammed. In this way, if the Counter has beenprogrammed for one byte counts (either most significantbyte only or least significant byte only) the other byte willbe zero.
M. Krishna Kumar
MM/M3/LU9a/V1/
Note that the CE cannot be written into, whenever a countis written, it is written into the CR.
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The Control Logic is also shown in the diagram.
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CLK n, GATE n, and OUT n are all connected to theoutside world through the Control Logic.
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The 8254 is a component
of the Intel Microcomputer Systems and interfaces in thesame manner as all other peripherals of the family.
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It is treated by the system's software as an array ofperipheral I/O ports; three are counters and the fourth is acontrol register for MODE programming.
