Wallace Tree Multiplier Verilog Code and Test Bench, Lecture notes of Very large scale integration (VLSI)

The verilog code and test bench for designing an (8x8)-bit wallace tree multiplier. The code includes the design of full adders, half adders, and the implementation of the wallace multiplier. The test bench includes input signals a and b, output signal out, and simulation of test cases with at least 4 different input combinations.

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2021/2022

Uploaded on 06/06/2022

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Assignment : 7
(8x8) bit Wallace Tree Multiplier
Pravallika Saladi - 119ec0013
Write Verilog program to design (8x8)-bit Wallace tree multiplier. Simulate the program with test cases (at least 4).
CODE:
//A Full adder with 3 inputs and 2 outputs(sum,carry)
module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry = ((a&b)| (b&c)|(c&a));
endmodule
//Half adder with 2 inputs and 2 outputs(sum,carry)
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry = (a&b);
endmodule
//Wallace multiplier 8x8 bits
module wallace(a,b,out);
input [7:0] a,b;
output [15:0] out;
wire [7:0] p0,p1,p2,p3,p4,p5,p6,p7;
//Partial Products we have total 8
assign p0 ={a[0]&b[7],a[0]&b[6],a[0]&b[5],a[0]&b[4],a[0]&b[3],a[0]&b[2],a[0]&b[1],a[0]&b[0]}; //Partial Product-1
assign p1 ={a[1]&b[7],a[1]&b[6],a[1]&b[5],a[1]&b[4],a[1]&b[3],a[1]&b[2],a[1]&b[1],a[1]&b[0]}; //Partial Product - 2
assign p2 ={a[2]&b[7],a[2]&b[6],a[2]&b[5],a[2]&b[4],a[2]&b[3],a[2]&b[2],a[2]&b[1],a[2]&b[0]}; //Partial Product-3
assign p3 ={a[3]&b[7],a[3]&b[6],a[3]&b[5],a[3]&b[4],a[3]&b[3],a[3]&b[2],a[3]&b[1],a[3]&b[0]}; //Partial Product-4
assign p4 ={a[4]&b[7],a[4]&b[6],a[4]&b[5],a[4]&b[4],a[4]&b[3],a[4]&b[2],a[4]&b[1],a[4]&b[0]}; //Partial Product-5
assign p5 ={a[5]&b[7],a[5]&b[6],a[5]&b[5],a[5]&b[4],a[5]&b[3],a[5]&b[2],a[5]&b[1],a[5]&b[0]}; //Partial Product-6
assign p6 ={a[6]&b[7],a[6]&b[6],a[6]&b[5],a[6]&b[4],a[6]&b[3],a[6]&b[2],a[6]&b[1],a[6]&b[0]}; //Partial Product-7
assign p7 ={a[7]&b[7],a[7]&b[6],a[7]&b[5],a[7]&b[4],a[7]&b[3],a[7]&b[2],a[7]&b[1],a[7]&b[0]}; //Partial Product-8
wire [15:0]pp0,pp1,pp2,pp3,pp4,pp5,pp6,pp7;
assign pp0 = {8'b0,p0}; //shift by 8 bits
assign pp1 = {7'b0,p1,1'b0}; //shift by 7 bits
assign pp2 = {6'b0,p2,2'b0}; //shift by 6 bits
assign pp3 = {5'b0,p3,3'b0}; //shift by 5 bits
assign pp4 = {4'b0,p4,4'b0}; //shift by 4 bits
assign pp5 = {3'b0,p5,5'b0}; //shift by 3 bits
assign pp6 = {2'b0,p6,6'b0}; //shift by 2 bits
assign pp7 = {1'b0,p7,7'b0}; //shift by 1 bits
//LEVEL-1
//CSA-1
half_adder mod01(pp0[1],pp1[1],s0,c0);
full_adder mod02(pp0[2],pp1[2],pp2[2],s1,c1);
full_adder mod03(pp0[3],pp1[3],pp2[3],s2,c2);
pf3
pf4

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Assignment : 7

(8x8) bit Wallace Tree Multiplier

Pravallika Saladi - 119ec

Write Verilog program to design (8x8)-bit Wallace tree multiplier. Simulate the program with test cases (at least 4). CODE: //A Full adder with 3 inputs and 2 outputs(sum,carry) module full_adder(a,b,c,sum,carry); input a,b,c; output sum,carry; assign sum=a^b^c; assign carry = ((a&b)| (b&c)|(c&a)); endmodule //Half adder with 2 inputs and 2 outputs(sum,carry) module half_adder(a,b,sum,carry); input a,b; output sum,carry; assign sum=a^b; assign carry = (a&b); endmodule //Wallace multiplier 8x8 bits module wallace(a,b,out); input [7:0] a,b; output [15:0] out; wire [7:0] p0,p1,p2,p3,p4,p5,p6,p7; //Partial Products we have total 8 assign p0 ={a[0]&b[7],a[0]&b[6],a[0]&b[5],a[0]&b[4],a[0]&b[3],a[0]&b[2],a[0]&b[1],a[0]&b[0]}; //Partial Product- assign p1 ={a[1]&b[7],a[1]&b[6],a[1]&b[5],a[1]&b[4],a[1]&b[3],a[1]&b[2],a[1]&b[1],a[1]&b[0]}; //Partial Product - 2 assign p2 ={a[2]&b[7],a[2]&b[6],a[2]&b[5],a[2]&b[4],a[2]&b[3],a[2]&b[2],a[2]&b[1],a[2]&b[0]}; //Partial Product- assign p3 ={a[3]&b[7],a[3]&b[6],a[3]&b[5],a[3]&b[4],a[3]&b[3],a[3]&b[2],a[3]&b[1],a[3]&b[0]}; //Partial Product- assign p4 ={a[4]&b[7],a[4]&b[6],a[4]&b[5],a[4]&b[4],a[4]&b[3],a[4]&b[2],a[4]&b[1],a[4]&b[0]}; //Partial Product- assign p5 ={a[5]&b[7],a[5]&b[6],a[5]&b[5],a[5]&b[4],a[5]&b[3],a[5]&b[2],a[5]&b[1],a[5]&b[0]}; //Partial Product- assign p6 ={a[6]&b[7],a[6]&b[6],a[6]&b[5],a[6]&b[4],a[6]&b[3],a[6]&b[2],a[6]&b[1],a[6]&b[0]}; //Partial Product- assign p7 ={a[7]&b[7],a[7]&b[6],a[7]&b[5],a[7]&b[4],a[7]&b[3],a[7]&b[2],a[7]&b[1],a[7]&b[0]}; //Partial Product- wire [15:0]pp0,pp1,pp2,pp3,pp4,pp5,pp6,pp7; assign pp0 = {8'b0,p0}; //shift by 8 bits assign pp1 = {7'b0,p1,1'b0}; //shift by 7 bits assign pp2 = {6'b0,p2,2'b0}; //shift by 6 bits assign pp3 = {5'b0,p3,3'b0}; //shift by 5 bits assign pp4 = {4'b0,p4,4'b0}; //shift by 4 bits assign pp5 = {3'b0,p5,5'b0}; //shift by 3 bits assign pp6 = {2'b0,p6,6'b0}; //shift by 2 bits assign pp7 = {1'b0,p7,7'b0}; //shift by 1 bits //LEVEL- //CSA- half_adder mod01(pp0[1],pp1[1],s0,c0); full_adder mod02(pp0[2],pp1[2],pp2[2],s1,c1); full_adder mod03(pp0[3],pp1[3],pp2[3],s2,c2);

full_adder mod04(pp0[4],pp1[4],pp2[4],s3,c3); full_adder mod05(pp0[5],pp1[5],pp2[5],s4,c4); full_adder mod06(pp0[6],pp1[6],pp2[6],s5,c5); full_adder mod07(pp0[7],pp1[7],pp2[7],s6,c6); half_adder mod08(pp1[8],pp2[8],s7,c7); //CSA- half_adder mod10(pp3[4],pp4[4],s00,c00); full_adder mod11(pp3[5],pp4[5],pp5[5],s11,c11); full_adder mod12(pp3[6],pp4[6],pp5[6],s22,c22); full_adder mod13(pp3[7],pp4[7],pp5[7],s33,c33); full_adder mod14(pp3[8],pp4[8],pp5[8],s44,c44); full_adder mod15(pp3[9],pp4[9],pp5[9],s55,c55); full_adder mod16(pp3[10],pp4[10],pp5[10],s66,c66); half_adder mod17(pp4[11],pp5[11],s77,c77); //LEVEL- //CSA- half_adder mod18(s1,c0,s21,c21); full_adder mod19(s2,c1,pp3[3],s22,c22); full_adder mod20(s3,c2,s00,s23,c23); full_adder mod21(s4,c3,s11,s24,c24); full_adder mod22(s5,c4,s22,s25,c25); full_adder mod23(s6,c5,s33,s26,c26); full_adder mod24(s7,c6,s44,s27,c27); full_adder mod25(pp2[9],c7,s55,s888,c888); //CSA- half_adder mod26(pp6[6],c11,s1111,c41); full_adder mod27(pp6[7],pp7[7],c22,s42,c42); full_adder mod28(pp6[8],pp7[8],c33,s43,c43); full_adder mod29(pp6[9],pp7[9],c44,s44,c44); full_adder mod30(pp6[10],pp7[10],c55,s45,c45); full_adder mod31(pp6[11],pp7[11],c66,s46,c46); full_adder mod32(pp6[12],pp7[12],c77,s47,c47); half_adder mod33(pp6[13],pp7[13],s48,c48); //LEVEL- //CSA- half_adder mod34(s22,c21,s11111,c11111); half_adder mod35(s23,c22,s22222,c22222); half_adder mod36(s24,c23,s33333,c33333); full_adder mod37(s25,c24,s1111,s44444,c44444); full_adder mod38(s26,c25,s42,s55555,c55555); full_adder mod39(s27,c26,s43,s66666,c66666); full_adder mod40(s888,c27,s44,s77777,c77777); full_adder mod41(s66,c888,s55,s88888,c88888); half_adder mod42(s77,s46,s99999,c99999); //LEVEL- //CSA- half_adder mod43(s22222,c11111,s111111,c111111); half_adder mod44(s33333,c22222,s222222,c222222); half_adder mod45(s44444,c33333,s333333,c333333); full_adder mod46(s55555,c44444,c41,s444444,c444444); full_adder mod47(s66666,c55555,c42,s555555,c555555); full_adder mod48(s77777,c66666,c43,s666666,c666666); full_adder mod49(s88888,c77777,c44,s777777,c777777); full_adder mod50(s99999,c88888,c55,s888888,c888888); full_adder mod51(s47,c99999,c46,s999999,c999999); half_adder mod52(s48,c47,ss111111,cc111111); half_adder mod53(pp7[14],c48,ss222222,cc222222); //LEVEL- //Carry Lookahead Adder half_adder mod54(s222222,c111111,ss0,cc0); full_adder mod55(s333333,c222222,cc0,ss1,cc1);

Command Prompt: GTKWAVE: