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Este documento detalla las características y el funcionamiento del procesador de texto sintetizado WTS701 de Winbond. Se incluyen informaciones sobre la configuración de las entradas y salidas, el protocolo de comunicación SPI y el modo de programación del dispositivo. Además, se explica cómo funciona la lista de abreviaciones y cómo personalizar la salida de texto.
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Publication Release Date May 2003
- 1 - Revision 3.
The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated between datasheet revisions.
The WTS701 is a high quality, fully integrated, single-chip Text-to-Speech solution that is ideal for use in applications such as automotive appliances, GPS/navigation systems, cellular phones and other portable products or accessories. The WTS701 product accepts ASCII (Unicode and Big5 for Mandarin) input via a SPI port and converts it to spoken audio via an analog output or digital CODEC output.
The WTS701 integrates a text processor, smoothing filter and multi-level memory storage array on a single-chip. Text-to-speech conversion is achieved by processing the incoming text into a phonetic representation that is then mapped to a corpus of naturally spoken word parts. The synthesis algorithm attempts to use the largest possible word unit in the appropriate context to maximize natural sounding speech quality. The speech units are stored uncompressed in a multi-level, non-volatile analog storage array to provide the highest sound quality to density trade-off. This unique, single-chip solution is made possible through Winbond’s patented multilevel storage technology. Voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality voice reproduction.
The chip can be programmed through the SPI port, allowing downloading of different languages and speaker databases when made available by Winbond.
AUX OUT
V (^) CCA V (^) SSAV (^) SSA V (^) SSD V (^) SSD V (^) CCD V (^) CCD
Power Conditioning
RAM
FLASH CODESTORE MEMORY (ROM)
SPI INTERFACE
REFERENCE GENERATION
MLS PHOENEME MEMORY
HIGH VOLTAGE GENERATION
PROCESSOR
13 BIT CODEC LINEAR/ 2’S COMPLEMENT
SS
MOSI MISO SCLK
MLS CONTROL LOGIC
VCLK
VDX
VFS
SP+ SP-
Spkr.AMP
AUXOUT AMP
CLOCK GENERATION
XTAL XTAL
ANALOG SIGNAL AUXIN AUX CONDITIONING AMP
*R/B
INT*
RESET
*CS*
ATT CAP
Figure 1. WTS701 Block Diagram.
Publication Release Date: May 2003
- 5 - Revision 3.
Figure 2. WTS701 Configuration for Digital (CODEC) Environment.
Figure 3. WTS701 Configuration for Analog Environment
HOST Controller
SS
MOSI MISO SCLK
VDX
VCLK
VFS
SP+ SP-
AUXIN
*R/B
INT*
*CS*
AUXOUT
Baseband Processor
CODEC
DIN
CL
FS
DOUT
HOST Controller
SS
MOSI MISO SCLK
VDX
VCLK
VFS
SP+ SP-
AUXIN
*R/B
INT*
*CS*
AUXOUT (^) Line out Line in
The following sections detail the pins of the WTS701 processor.
Table 1 shows all the pins and the signals that use them in different configurations. It also shows the type and direction of each signal. Figure 4 shows the physical pin out of the 56-pin TSOP package.
1 2 3 4 5 6 7 8 9
10 11 12 13
VS S A
W TS
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VCLK VF S VDX M IS O XT AL XT AL VS S D VS S D VCC D VCC D INT
M OS I S S
S CLK NC NC NC NC NC NC NC NC
NC
NC 56
C S
R/B
R ES ET
AUXOUT
AUXIN
VC C A
S P +
VS S A
S P -
AT T C AP NC NC
NC
NC
NC NC
NC
NC NC NC
NC
NC
NC NC
NC
NC
NC NC
NC
NC
VS S A
Figure 4. 56-pin TSOP Package Connection Diagram.
27 RESET I Global reset signal. 40 ATTCAP I/O AutoMute Capacitor Pin. Should have a 4.7uF capacitor to V (^) SSA. 42 SP- O Differential Negative Speaker Driver Output. 46 SP+ O Differential Positive Speaker Driver Output. 48 VCCA P Positive Analog Voltage Supply pin. This pin supplies the LOW level audio sections of the device. It should be carefully bypassed to Analog Ground to ensure correct device operation. 52 AUXIN I Analog input pin. This pin should be capacitively coupled. See page 73 for example. 54 AUXOUT O Analog Output for single ended output from the device. 1,17- 24,28- 35,37- 39,41,43, 45,47,49- 51,53,55- 56
NC Not Connected – must be floating.
Note: TYPE I:Input, O:Output, I/O bi-directional, P:Power, G:Ground
Publication Release Date: May 2003
- 11 - Revision 3.
As a real System-On-Chip solution, the WTS701 performs the overall control functions for host controller and text-to-speech processing.
The WTS701 system architecture consists of the following functions:
The WTS701 system performs text-to-speech synthesis based on concatenative samples. The units for concatenation can vary from whole words down to phoneme units. The convention is that the larger the sub-word unit used for synthesis the higher the quality of the speech output. A corpus of pre-recorded words is stored in Winbond’s patented multilevel storage (MLS) memory and a mapping of the various sub-word parts is held in a lookup table. The speech creation is achieved by concatenation of these speech elements to produce words. The system process flow is shown in Figure 5.
Text Normalization
Words to Phoneme
Phoneme Mapper
Memory
Digital output
Analog output
Figure 5. WTS701 System Process Flow.
Publication Release Date: May 2003
- 13 - Revision 3.
The following sections describe the physical pin properties and the timing associated with the physical
interface to the device. Note that all input pins are 3V and 5V tolerant, except for the CS signal which is only 3V tolerant.
7.2.1 Clocking Requirements
The WTS701 processor can receive its clock from either an external clock source or a crystal oscillator. The XTAL1 and XTAL2 pins provide the crystal interface to the device. The clock to the WTS701 processor is configured by a clock configuration register, which must be set by the host processor during the initialization phase. Figure 6 below shows how to connect the WTS701 to a crystal oscillator. An external clock can be connected to the WTS701 providing the clock source for the system, as shown in Figure 6.
WTS
XTAL
XTAL
WTS
XTAL
XTAL
CLK IN
X
C
C
C1 = C2 = 15pF X1 = 24.576MHz
Figure 6. Clock Generation.
Suggested Crystal Specification:
F = 24.576 MHz Fundamental Mode Operation CL = 16 pF ESR = 60 Ω maximum
7.2.2 Power Down Mode
Upon application of power, the WTS701 will enter the RESET state and then be in a POWER DOWN state. In the POWER DOWN mode, only Class0 SPI commands are valid. (See subsection 7.3.1). The Power Down status of the device can be determined with a RDST (Read Status) command, specified by the RDY bit in STATUS BYTE 0.
Issuing the PWDN (Power Down) command to the WTS701 processor will return the processor to the POWER DOWN mode. In POWER DOWN mode the external crystal oscillator is shut off and the processor is deactivated. POWER DOWN mode is exited by issuing a PWUP (Power Up) command to the WTS701. The PWUP command should be preceded by a SCLC (Set Clock) command to ensure correct clock configuration.
7.2.3 Power and Grounding
The WTS701 can operate over 2.7V to 3.3V supply voltage range. The power supply and ground pins (V CCA, V CCD , V SSA, V SSD ) should be carefully bypassed as close to the chip as possible to ensure high quality audio. In addition, ATTCAP pin should have a 4.7 μF capacitor connected to ground. This pin must NOT be left floating. The pins that are marked as NC (Not Connected), MUST be left floating.
VCCA, VCCD (Voltage Inputs)
To minimize noise, the analog and digital circuits in the WTS701 device use separate power busses. These +3.0 V busses lead to separate pins. For optimal noise immunity, tie the V (^) CCD pins together as close as possible and decouple both supplies as near to the package as possible.
VSSA, VSSD (Ground Inputs)
The WTS701 series utilizes separate analog and digital ground busses. The analog ground (V (^) SSA) pins should be tied together as close to the package as possible and connected through a low- impedance path to power supply ground. The digital ground (VSSD ) pin should be connected through a separate low-impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3Ω. The backside of the die is connected to VSSD through the substrate resistance.
NC (Not Connect)
These pins MUST not be connected to the board at any time. Connection of these pins to any signal, ground or VCC may result in incorrect device behavior or cause damage to the device.
7.2.5 Flow Control Interface
In addition to the SPI interface, the WTS701 has two control lines to facilitate data transfer and host
communications. The INT (interrupt) pin is used by the WTS701 to request an interrupt service from the host controller. The interrupt types that the device generates are controlled by the
communications control register command (SCOM). The R/ B^ (ready/busy) pin is used to control the flow of data across the SPI bus. When this signal is HIGH, the device can accept more data. When it is LOW, SPI transactions must be paused or terminated.
INT (Interrupt)
INT is an open drain output pin. The WTS701 interrupt pin goes LOW and stays LOW when an interrupt event has occurred, as defined by the SCOM command. The interrupt is cleared when a RINT (read interrupt) command is executed. The status register defines what type of interrupt has occurred.
R/ B (Ready/Busy Signal)
The R/ B line is an output open drain pin used to control data transfer rate across the SPI port. The line is used as a handshake signal to the SPI Master to indicate when the device is ready for more data. When HIGH, the master is free to send more data. When LOW, the device is busy and cannot accept more data.
7.2.6 The CODEC Interface
The WTS701 provides an on chip interface for digital environment systems, supporting slave CODEC interface mode. The WTS701 CODEC interface is controlled by an external source hence the WTS701 only transmits data. Thus, it is effectively an analog-to-digital converter. Each analog sample is converted to 10 bit digital word. This digital word is transmitted with the MSB first. Since the host expects either 13 or 16 bit data in the short frame format, either three or six zeros are appended as the LSB. It interfaces to the baseband CODEC via the VCLK, VFS and VDX lines. Refer to Figure 2, for more information about the connection between the WTS701 and a CODEC.
All Input pins are 3V and 5V tolerant.
The following is a description of the WTS701 CODEC interface signals:
VCLK (CODEC Clock Line)
The CODEC clock line supplies the sampling clock to the internal CODEC. This is a digital input and expects a 512kHz—2.048MHz clock.
Publication Release Date: May 2003
- 17 - Revision 3.
VFS (CODEC Synchronization Line) The CODEC synchronization line supplies a frame synchronization signal to the internal CODEC. This is a digital input. After receipt of a synchronization pulse, the CODEC will output data on the VDX line. The VFS line expects an 8kHz sample rate and supports both short frame and long frame synchronization signal.
VDX (CODEC Data Transmit Line)
The CODEC data transmit line is a digital output that places digital audio data onto the CODEC bus. The line is in a tri-state condition until the device is due to transmit data. The data output from the VDX line is selected by the SCOD Command. When WTS701 places data on the VDX line, it is required that the VFS line should be in tri-state condition when another device is connected to the CODEC as well.
7.2.7 The Analog Interface
signal to be fed through the WTS701 chip to either output device. The command SAUD configures the analog path. A digitally controlled attenuator provides volume control via the SVOL command.
The following is a description of the analog pins:
AUXIN (Analog Input)
The AUXIN is an additional audio input to the WTS701. This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB) (See Table 2). Additional gain is available in 3 dB steps (controlled by the SAUD Command) up to 9 dB. The use and equivalent circuit of the input amplifier is shown in Figure 7. (Must be AC coupled)
Ra
Internal to the device Rb
CCOUP = 0.1 μF
1
Figure 7. AUXIN Input Amplifier.
Publication Release Date: May 2003
- 19 - Revision 3.
T (^) res et
T (^) re s et > 0.5μ s
R ESET
Figure 8. Reset Condition Timing.
The WTS701 is controlled by a series of SPI transactions to send commands to the device. The general format of an SPI transaction is shown in Figure 9. A transaction is always started by sending a command word. The command word consists of a command byte followed by a command data byte. At the same time, the status register is shifted out on the MISO line. What follows depends on what command is sent. The general case is that following the command word, up to n -bytes of data can be
sent to the device and n- bytes can be read from the device. An SPI transaction is finished when SS is returned to the HIGH condition.
DATA1 DATAn
DATA1 DATAn
DATA
DATA
CMD DATA
STATUS BYTE 1
CMD BYTE
STATUS BYTE 0
MOSI
MISO
MSB LSB
time
7
7
7
7
7
7 7
7
0 0 0 0
0 0 0 0
Figure 9. SPI Transaction Format.
7.3.1 Command Classes
The SPI transactions to the WTS701 fall into four classes. The four classes represent variations in how the command, and any associated data, is handled. The class of a command is defined by the two most significant bits of the command byte. A summary of the command classes is given below
Class 0 Commands
These are commands that are executed irrespective of the state of the WTS701. That is, the command will execute even if the device is busy or powered down. These commands are executed internally by a hardware command interpreter. All commands not of class 0 require that the WTS be in a powered up state. Example of class 0 command is the Read Status (RDST) command.
Class 1 Commands
Class 1 commands require interpretation by the internal firmware of the WTS701. Class 1 commands consist only of a command byte and command data byte. Any further data sent in a transaction is ignored. Class 1 commands are most often used for setting a configuration register in the device or sending commands that have no data such as the conversion pause (PAUS) command.
Class 2 Commands
Class 2 commands have associated data. After the command word, any data bytes following are
loaded into an internal FIFO buffer for processing. If this FIFO becomes full, the R/ B signal is asserted (LOW) indicating that the host must pause data transfer. An alternative to monitoring the
R/ B line, the R/ B bit of the status register can be monitored instead (see subsection 7.3.2) or via the
RDST command. The R/ B bit cannot be used for intra-byte flow control, e.g. if a string of characters is sent, only every other byte is checked.
Class 3 Commands
Class 3 commands have data to return to the host. The R/ B line will go to busy immediately following the command word indicating that the WTS701 is fetching the requested data. Data is put into the BCNT0 and BCNT1 (see subsection 7.3.4) registers and is read out in the two subsequent bytes after
R/ B is released. If more than two bytes are returned from the command, R/ B will again be asserted until data is ready to read. The primary Class 3 commands are to read the contents of internal configuration registers such as RREG command.
