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Assembly language

Marta Ruiz Llata Luis Entrena

Machine code

0000 0000 0000 0000 0000 0000 0000 0000 0101 0001 0010 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

Move the contents at the address specified by the BSR and the operand (0x27) to WREG

movf 0x27,0,

mnemonic operands

2

An assembly language instruction directly corresponds to an instruction in machine language

PIC18 instruction set

• Standard set of 75 PIC18 core instructions
• Most instructions are a single program memory word (16 bits), except 4 instructions that require 2 program memory locations
• The instruction set is highly orthogonal and is grouped into four basic categories:  Byte-oriented operations  Bit-oriented operations  Literal operations  Control operations

Complete information in Section 24 of Datasheet

PIC18 instruction set

• Most byte-oriented instructions have three operands:  f: file register  d: Destination of the result: WREG (d = 0) or file register (d = 1)  a: Bank: Access bank (a = 0) or specified by BSR (a = 1)
• All bit-oriented instructions have three operands:  f: file register  b: bit in file register  a: Bank: Access bank (a = 0) or specified by BSR (a = 1)

Example of detailed instruction

description

Data memory

BSR: Bank Select Register SFR: Special Function Register GPR: General Purpose Register

8

Examples incf f,d,a : incf 0x27,0,0 WREG[0x027]+ incf 0x27,1,0 [0x027][0x027]+ incf 0xE0,0,0 WREG[0xFE0]+ incf 0xE0,1, if BSR=0x01 [0x1E0][0x1E0]+ if BSR=0x0F [0xFE0][0xFE0]+

Data transfer instructions

• MOVLW k ; Move literal to WREG  k → W MOVLW 0x5A
• MOVLB k ; Move literal to BSR  k → BSR MOVLB 5
• LFSR f, k ; Load 12 bit literal in FSRf  k → FSRf LFSR 2, 0x3AB

Data transfer instructions

• MOVF f, d, a ; Move register f to WREG  f → dest MOVF REG, 0, 0
• MOVWF f, a ; Move WREG to register f  (W) → f MOVWF REG, 0
• MOVFF fs, fd ; Move register fs to fd (full address)  (fs) → fd MOVFF REG1, REG

Arithmetic instructions

• ADDLW k ; Add literal to WREG  (W) + k → W ADDLW 0x
• ADDWF f, d, a ; Add WREG to register f  (W) + (f) → dest ADDWF REG, 0, 0
• ADDWFC f, d, a ; Add WREG and Carry bit to register f  (W) + (f) + (C) → dest ADDWFC REG, 0, 1

Arithmetic instructions

• SUBLW k ; Subtract WREG from literal  k – (W) → W SUBLW 0x
• SUBWF f, d, a ; Subtract WREG from register f  (f) – (W) → dest SUBWF REG, 1, 0
• SUBFWB f, d, a ; Subtract register f from WREG with Borrow  (W) – (f) – (C’) → dest SUBFWB REG, 1, 0
• SUBWFB f, d, a ; Subtract WREG from register f with Borrow  (f) – (W) – (C’) → dest SUBWFB REG, 1, 0

Increment / Decrement instructions

• INCF f, d, a ; Increment register f  (f) + 1 → dest INCF CNT, 1, 0
• INCFSZ f, d, a ; Increment f, Skip if 0
• INFSNZ f, d, a ; Increment f, Skip if not 0
• DECF f, d, a ; Decrement f
• DECFSZ f, d, a ; Decrement f, Skip if 0
• DCFSNZ f, d, a ; Decrement f, Skip if not 0

Logic instructions

• COMF f, d, a ; Complement register f  NOT (f) → dest
• ANDLW k ; AND literal with WREG  (W) AND k → W ANDLW 0x05F
• ANDWF f, d, a ; AND WREG with register f  (W) AND (f) → dest ANDWF REG, 0, 0
• IORLW k ; OR literal with WREG
• IORWF f, d, a ; OR WREG with register f
• XORLW k ; XOR literal with WREG
• XORWF f, d, a ; XOR WREG with register f

Comparison instructions

• TSTFSZ f, a ; Test f, Skip if 0  skip if f = 0 HERE TSTFSZ CNT, 1 NZERO : ZERO :
• CPFSEQ f, a ; Compare f with WREG, Skip if f = W  (f) – (W), skip if (f) = (W) HERE CPFSEQ REG, 0 NEQUAL : EQUAL :
• CPFSGT f, a ; Compare f with WREG, Skip if f > W
• CPFSLT f, a ; Compare f with WREG, Skip if f < W

Branch instructions

• BRA n ; Unconditional branch  (PC) + 2 + 2n → PC HERE BRA Jump
• GOTO k ; Unconditional branch  k → PC<20:1> GOTO THERE