registre32.vhd Sun Nov 12 22:47:03 2017
Page 1
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity registre32 is
5 port(I:in std_logic_vector(31 downto 0);
6 E,RST,CLK : in std_logic;
7 O : out std_logic_vector(31 downto 0));
8 end registre32;
9
10 architecture Behavioral of registre32 is
11
12 begin
13 process(CLK)
14 begin
15 if(rising_edge(CLK)) then
16 if(RST = '1') then
17 O <= (others => '0');
18 elsif(E = '1') then
19 O <= I;
20 end if;
21 end if;
22 end process;
23
24 end Behavioral;