TESTBECH
COMPONENT Proef4
PORT( CE : IN STD_LOGIC;
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
TC : OUT STD_LOGIC;
CEO : OUT STD_LOGIC;
Q3 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q0 : OUT STD_LOGIC);
END COMPONENT;
SIGNAL CE : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
SIGNAL CLR : STD_LOGIC;
SIGNAL TC : STD_LOGIC;
SIGNAL CEO : STD_LOGIC;
SIGNAL Q3 : STD_LOGIC;
SIGNAL Q2 : STD_LOGIC;
SIGNAL Q1 : STD_LOGIC;
SIGNAL Q0 : STD_LOGIC;
BEGIN
UUT: Proef4 PORT MAP(
CE => CE,
CLK => CLK,
CLR => CLR,
TC => TC,
CEO => CEO,
Q3 => Q3,
Q2 => Q2,
Q1 => Q1,
Q0 => Q0
);