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The instructions for lab 5 of the computer architecture i course, where students are required to expand an instruction set architecture (isa) and code in assembly. The lab aims to provide students with expertise in comparing and contrasting different computer architectures, and understanding the impact of various architectural decisions on code execution time. The lab involves working with a 6-instruction processor and mips datapath, converting assembly code to machine code, simulating code, and observing changes in the register file and memory. Students are also required to write their own self-modifying code and compare the performance of 6-instruction code and mips code.
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Lab 5: Expanding an ISA and Coding in Assembly (50 points) Assigned: Week of October 29th. Due: Week of November 5th
Looking back to big pictures objectives of class, the purpose of this lab is to:
Background:
What do I do?
Questions:
Background: Here, you’ll need to translate some pseudocode to (i) a set of equivalent 6-instruction processor instructions and (ii) a set of equivalent MIPS instructions. Armed with both instruction sequences, we can quantify the number of clock cycles to execute each snippet – and see how much time it takes to perform this function-level task given two different instruction set architectures^1.
What do I do?
a = [4 12 9 24 17 -1]; i = 0; max = -1; while(a[i] != -1) if(a[i] > max) max = a[i]; i++;
Questions:
Datapath
RF_Rp_addr
RF_Rq_addr
RF_Rp_zero
RF_W _addr
D_addr
D_rd D_wr
RF_s 1
RF_W _data
RF_s 0
alu_s 1 alu_s 0
addr (^) D rd wr
256x
16 x RF
16-bit 3x
W _data R_data
Rp_data Rq_data
W _data W _addr W _wr Rp_addr Rp_rd Rq_addr Rq_rd
0
16
16
16 16 16
16
s 1 s 0
2 1
s 1 A^ B s 0 ALU
4
4
4
=
8
8
PC ld clrup
8 IR Id
Controller
Controlunit
a+b-
16
IR[7..0]
PC_ld PC_clrPC_inc IR_ld
s 1 0 0 1
s 0 0 1 0
ALU operation passA through A+B A-B
8
D_addr_sel
0 PC_addr (^1)
8-bit 2x
Figure 1: A simple processor with a unified memory.