Lab 5 of Computer Architecture I Course: Expanding an ISA and Coding in Assembly, Summaries of Computer Architecture and Organization

The instructions for lab 5 of the computer architecture i course, where students are required to expand an instruction set architecture (isa) and code in assembly. The lab aims to provide students with expertise in comparing and contrasting different computer architectures, and understanding the impact of various architectural decisions on code execution time. The lab involves working with a 6-instruction processor and mips datapath, converting assembly code to machine code, simulating code, and observing changes in the register file and memory. Students are also required to write their own self-modifying code and compare the performance of 6-instruction code and mips code.

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CSE30321 Computer Architecture I
Lab 5: Expanding an ISA and Coding in Assembly (50 points)
Assigned: Week of October 29th. Due: Week of November 5th
1 Introduction
Looking back to big pictures objectives of class, the purpose of this lab is to:
Begin to see how the fundamental components of a modern microprocessor work together.
Give you expertise in comparing and contrasting different computer architectures. A hardware implementa-
tion of the 6-instruction processor would be different from a hardware implementation of the MIPS datapath
discussed in class. Memory is accessed in different ways, MIPS provides more instruction types ... which
implies a more complex datapath, etc. These issues will all ultimately impact the time required to execute
code written in a high-level language as well as how it is executed.
2 Insight into Self Modifying Code
Background:
Secs. 2 and 3 of the lab are designed to show you how the 6-instruction processor instruction set architecture
can be used to execute more complex high-level language code even with a limited number of instructions
and a relatively simple datapath. In Sec. 2, we’ll first see how more complex code can be executed with just
6-instruction. In Sec. 3 we’ll quantitatively compare 6-instruction code to an equivalent MIPS version.
What do I do?
1. Open ISE and create a new project called “lab5” in an empty directory. Download and extract the zipped
Verilog files from the course web page into a different directory. In ISE, add the Verilog files by clicking “Add
Copy of Source...” under the ”Project” menu.
Note: This version of the processor is slightly different from the one in the previous labs. See Appendix for
more details about this processor design.
2. Download the file ArrayAccess.s from the course web page. Convert the assembly code to machine code. We
have provided a new assembly/simulator for the 6-instruction processor to aid this process. (The Java-based
simulator does not work with self-modifying code. See the course web site for instructions on how to use the
Linux-based assembler/simulator.)
3. Put the machine code in the memory by modifying “comb mem.v” (values are in hexadecimal).
4. Simulate the code such that the loops are executed three times. The output ”R0 out” can be disregarded until
later in the lab.
5. Whenever you observe changes in the register file and memory, record the time when this happens (i.e.,
during the execution of which instruction), the register and/or memory location, as well as the corresponding
contents before and after the change.
Questions:
(A) What does the sixth instruction try to achieve?
(B) Based on your observations, describe what this code snippet accomplishes.
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CSE30321 Computer Architecture I

Lab 5: Expanding an ISA and Coding in Assembly (50 points) Assigned: Week of October 29th. Due: Week of November 5th

1 Introduction

Looking back to big pictures objectives of class, the purpose of this lab is to:

  • Begin to see how the fundamental components of a modern microprocessor work together.
  • Give you expertise in comparing and contrasting different computer architectures. A hardware implementa- tion of the 6-instruction processor would be different from a hardware implementation of the MIPS datapath discussed in class. Memory is accessed in different ways, MIPS provides more instruction types ... which implies a more complex datapath, etc. These issues will all ultimately impact the time required to execute code written in a high-level language – as well as how it is executed.

2 Insight into Self Modifying Code

Background:

  • Secs. 2 and 3 of the lab are designed to show you how the 6-instruction processor instruction set architecture can be used to execute more complex high-level language code – even with a limited number of instructions and a relatively simple datapath. In Sec. 2, we’ll first see how more complex code can be executed with just 6-instruction. In Sec. 3 we’ll quantitatively compare 6-instruction code to an equivalent MIPS version.

What do I do?

  1. Open ISE and create a new project called “lab5” in an empty directory. Download and extract the zipped Verilog files from the course web page into a different directory. In ISE, add the Verilog files by clicking “Add Copy of Source...” under the ”Project” menu. Note: This version of the processor is slightly different from the one in the previous labs. See Appendix for more details about this processor design.
  2. Download the file ArrayAccess.s from the course web page. Convert the assembly code to machine code. We have provided a new assembly/simulator for the 6-instruction processor to aid this process. (The Java-based simulator does not work with self-modifying code. See the course web site for instructions on how to use the Linux-based assembler/simulator.)
  3. Put the machine code in the memory by modifying “comb mem.v” (values are in hexadecimal).
  4. Simulate the code such that the loops are executed three times. The output ”R0 out” can be disregarded until later in the lab.
  5. Whenever you observe changes in the register file and memory, record the time when this happens (i.e., during the execution of which instruction), the register and/or memory location, as well as the corresponding contents before and after the change.

Questions:

  • (A) What does the sixth instruction try to achieve?
  • (B) Based on your observations, describe what this code snippet accomplishes.

3 Writing Your Own Self Modifying Code

Background: Here, you’ll need to translate some pseudocode to (i) a set of equivalent 6-instruction processor instructions and (ii) a set of equivalent MIPS instructions. Armed with both instruction sequences, we can quantify the number of clock cycles to execute each snippet – and see how much time it takes to perform this function-level task given two different instruction set architectures^1.

What do I do?

  1. Write an assembly program using the six instruction set discussed in class plus the instructions you have added in the previous labs. (Let’s call this program MaxFinder.s.) The MaxFinder program steps through a variable length array stored in consecutive memory locations and determines which of the elements is the largest. The array is terminated by the element containing -1. The psuedocode for the MaxFinder program appears below:

a = [4 12 9 24 17 -1]; i = 0; max = -1; while(a[i] != -1) if(a[i] > max) max = a[i]; i++;

  1. You must use a loop structure to step through the array. To accomplish this, you should consult the code snippet which you stepped through in the previous section. Specifically, this version of MaxFinder requires self-modifying code to allow for the use of a while loop. Self-modifying code takes advantage of the ability to modify instructions in the memory (as you have seen in the first part of this lab). In this way a loop can be created by changing instructions to access sequential locations in memory.
  2. Make sure that at the end of executing MaxFinder, the maximum value in the array is stored in register file location 0 (RF[0] = max). The output from the processor ”R0 out” is used simply to make it easier for you (and the TAs) to see the maximum value in the simulation waveforms.
  3. To end a program execution cleanly, we have added a new instruction, END, to the ISA. The opcode for this instruction is “1111”. Please use this instruction to end your program.
  4. Test your MaxFinder program with the new Linux-based assembler/simulator. (Again, the Java-based sim- ulator does not work with self-modifying code.) See the course web site for instructions on how to use the Linux-based assembler/simulator. Record the contents of the register file and memory locations at the end of the execution.

Questions:

  • (C) Assume that the array contains 10 elements and the 11th one contains -1. Based on the timing data of your processor implementation (which you have collected in the previous labs), calculate how many cycles it takes to execute your MaxFinder program. You need to take any wait states in the Verilog controller into account. Show your work.
  • (D) Write a sequence of MIPS instructions that will perform the functions given by the psuedo-code above:
  • (E) Assuming the cycle counts associated with the MIPS multi-cycle implementation, how long would it take to execute the MIPS sequence?
  • (F) Compare and contrast the 6-instruction code and the MIPS code. (Things to consider: Quantitatively, which performs better? Why? Hint: go back to CPU time equation in Lecture 17 review)
  • (G) Briefly discuss the pros and cons of self-modifying code. (^1) Note: Be sure you understand what the term “Instruction Set Architecture” means in this context.

Datapath

RF_Rp_addr

RF_Rq_addr

RF_Rp_zero

RF_W _addr

D_addr

D_rd D_wr

RF_s 1

RF_W _data

RF_s 0

alu_s 1 alu_s 0

addr (^) D rd wr

256x

16 x RF

16-bit 3x

W _data R_data

Rp_data Rq_data

W _data W _addr W _wr Rp_addr Rp_rd Rq_addr Rq_rd

0

16

16

16 16 16

16

s 1 s 0

2 1

s 1 A^ B s 0 ALU

4

4

4

=

8

8

PC ld clrup

8 IR Id

Controller

Controlunit

a+b-

16

IR[7..0]

PC_ld PC_clrPC_inc IR_ld

s 1 0 0 1

s 0 0 1 0

ALU operation passA through A+B A-B

8

D_addr_sel

0 PC_addr (^1)

8-bit 2x

Figure 1: A simple processor with a unified memory.