10 Instruction Sets - Faculty Websites, Slides of Architecture

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William Stallings Computer Organization and Architecture 8 th^ Edition

Chapter 10

Instruction Sets:

Characteristics and Functions

Instruction Set = The complete collection of instructions that are recognized by a CPU.

Representations:

• Machine code (Binary/Hex)
• Assembly code (Mnemonics)

Example (IAS – see ch.2):

00000101 0000000011 ADD M(3)

Where are the operands stored?

• In the instruction itself —immediate addressing
• Main memory —or virtual memory or caches, but this is transparent to the CPU
• CPU register
• I/O device —If memory-mapped, it’s just another address

00000101 0000000011 ADD M(3)

Instruction Cycle State Diagram (ch.3)

High-level language and assembly language

X = X + Y

compiles into:

• Load register A with contents of memory address 513
• Add reg. A w/contents of mem. addr. 514
• Store reg. A into mem. addr. 513

Conclusion: assembly is closer to the hardware.

Instruction Types

• Data processing (ALU)
• Data storage (main memory)
• Data movement (I/O)
• Program flow control

Number of Addresses (b)

• 2 addresses —One address doubles as operand and result —PDP-11 had ADD B,A (p.72) —Reduces length of instruction — Requires some extra work or specialized hardware: Temporary storage to hold some results … although synchronization with a CLK usually solves the problem elegantly:

Source: http://web.njit.edu/~gilhc/ECE394/ECE394-V.htm

Number of Addresses (c)

• 1 address —Implicit second address —Usually a register (accumulator) —Common on early machines

How Many Addresses

• More addresses —More complex (powerful?) instructions —More registers - Inter-register operations are quicker —Fewer instructions per program
• Fewer addresses —Less complex (powerful?) instructions —More instructions per program —Faster fetch/execution of instructions

Temporary memory location (a.k.a. variable)

Design Decisions (1)

• Operation repertoire —How many ops? —What can they do? —How complex are they?
• Data types
• Instruction formats —Length of op code field —Number of addresses

Design Decisions (2)

• Registers —Number of CPU registers available —Which operations can be performed on which registers?
• Addressing modes, i.e. how do we get to the operands (later…)
• RISC v CISC

Review / reading assignment (will also cover in this week’s lab)

Ch.9 sections:

Please follow all examples with pencil and paper (notebook!)

QUIZ: Problem 10.6 / 386

Write programs to compute and store result in X, on machines with instructions featuring:

• 0 addresses
• 1 address
• 2 addresses
• 3 addresses

D E F

A B C