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Homework 3 - Digital Systems Design
Problem 1
The following two Moore state machines interact with one another. Complete the timing diagram below for the two state machines. Assume the flip-flops trigger on the positive edge and there exists a small amount of delay for each transition. If an output is not shown on the state diagram, assume it is deasserted. Show the timing information for GO and DONE, however just write the state name for “main state” and “sub state”.
Reset
Clk
“main”
GO
“sub”
state
state
DONE
m GO
idle DONE
m
m
m
s
s
DONE
DONE
GO
GO
Reset (^) Reset
Problem 2
Develop a muti-module verilog description for the following schematic. Describe each unique block in the system using a unique .v file. Then develop a top-level module that calls each of the lower level modules and connects them appropriately. Reuse your verilog descriptions whenever possible. Design a test bench that will verify your design. Be sure to turn in a printout of each of your .v files, your testbench file, and an annotated waveform proving that your solution works correctly.
Problem 3
Write the verilog description of the state diagram for the lock problem in Homework 1. Use the Meely solution and encode your states using a binary representation. (Please start with our solu- tion posted on the web site rather than your own solution to the state diagram).Verify that your description is correct using a testbench file.
ADDER
REGISTER
Reset Clk
X Y
Sum
s1 s
COUNTER
Q
Q
Clk
Reset
s0 s
R
clock
A B C D W X Y Z
After the first clock cycle, register “B” should be zero. After the third clock cycle, register “A” should be ‘h03. After the fourth clock cycle, register “B” should be ‘hFF.
After the fifth clock cycle, register “A” should be ‘h02.
(a) Step through the following input stream, like the example above, showing the contents of both registers at the end of each clock cycle. Assume that R was asserted in the clock period prior to the beginning of the stream.
R asserted, then: FF FF FE FF FD FF FC FB F7 F9 …
(b) One way to implement this circuit is with a control unit (CU) that communicates with a data unit (DU). List the responsibilities of each unit for accomplishing the overall task. Explain why you chose to place each responsibility in each unit.
(c) Draw a state diagram for the CU and a schematic using LSI blocks for the DU.
(d) Implement the CU and the DU as separate Verilog modules in separate files. Attach a copy of your code.
(e) Write a test bench for your implementation. Attach a copy of the testbench and explain why the testbench is adequate for testing your design.
(f) Run your testbench and produce waveform output that demonstrates a successful test sequence. Annotate your plot to show what is happening.
