8088 Pin Assignment - Microprocessors and Computer Systems - Lecture Slides, Exercises of Microprocessors

Download 8088 Pin Assignment - Microprocessors and Computer Systems - Lecture Slides and more Exercises Microprocessors in PDF only on Docsity!

8088 Pin Assignment

Pin Layout of the 8088

Microprocessor

• Nine pins have functions which depend

on the state of

=high -- 8088 operates in

MINIMUM MODE

=low -- 8088 operates in

MAXIMUM MODE

• Minimum mode: - 8088 directly

generates the control signalsnecessary for accessing memory andIO ports.

• Maximum mode:- external support

chips are used to generate controlsignals; the processor can work in asystem containing other processors

MX

MN/

MX

MN/

MX

MN/

GND

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

AD

9

AD

10

AD

11

AD

12

AD

13

AD

14

AD

15

AD

16

NMI

17

INTR

18

CLK

19

GND

20

40

Vcc

39

A

38

A16/S

37

A17/S

36

A18/S

35

A19/S

3433323130292827262524232221

MX

MN/RD TESTREADYRESET

40 LEAD

8088 CPU

SS

(High)

HOLD

)

GT /

RQ (

HLDA

)

GT /

RQ (

WR

)

LOCK (

M

IO/

)

S (

R

DT/

)

S (

DEN

)

S (

ALE

(QS0)

INTA

(QS1)

Min Mode

(Max Mode)

Unique Minimum-mode Signals

Minimum mode signals (MN/

= V

CC

)

Name

Function

Type

HOLD

Hold

request

Input

HLDA

Hold

acknowledge

Output

Write control

Output,3-state

IO/memory control

Output,3-state

Data transmit/receive

Output,3-state

Data enable

Output,3-state

Status line

Output,3-state

ALE

Address

latch

enable

Output

Interrupt acknowledge

Output

MX

WR

M

IO/

R

DT/ DEN SSO INTA

Unique Maximum-mode Signals

Maximum mode signals (MN/

= GND)

Name

Function

Type

Request/grant bus

access control

Bidirectional

Bus priority lock

control

Output, 3-state

Bus cycle status

Output, 3-state

QS1, QS

Instruction queue

status

Output

MX

LOCK

S

S

/

RQ

GT

1, 0

Maximum-Mode of 8088

a

8288 Bus Controller

`

In maximum-mode, the signal to control memory, I/O, and interruptinterface is produced by 8288.

`

are no longer produced by

8088, instead 8288 generates the following signals

INTA

and

ALE,

DEN

R

DT/

M

IO/

WR

MRDCMWTCAMWCIORCIOWCAIOWC INTA

-- memory read command-- memory write command-- advanced memory write command-- I/O read command-- I/O write command-- advanced I/O write command-- interrupt acknowledge command

Bus Status Codes

Status Inputs

S

S

CPU Cycle

8288

Command

0

0

0

Interrupt

Acknowledge

INTA

0

0

1

Read I/O Port

IORC

0

1

0

Write

I/O

Port

AIOWC ,

IOWC

0

1

1

Halt

None

1

0

0

Instruction

Fetch

MRDC

1

0

1

Read

Memory

MRDC

1

1

0

Write

Memory

AMWC

MWTC

,

1

1

1

Passive

None

S

a

8288 produces the commands according to the output

bits

from 8088.

0

1

2

S

S

S

CPU 8088

S

0 S

1 S

2

Bus

Controller

8288

command

(In maximum-mode)

Pin Diagram

386DX processor view from pin side

Top view for 386SX processor

Minimum Mode System BlockDiagram and Pin Connections

V

cc

V

cc

GND

GND Address /data

Address

Data

IR

0-

CLK

MX

MN/

READY

M

IO/

RESET

RD WR

8088

INTA

CPU

R

DT/DENALE

A

8 -A

19

INTR

T OE

8286 Transceiver

EN

8259A Interruptcontroller INT

STBOE 8282 Latch

(1, 2 or

WEOE

2142 RAM (2)

OE

27162 PROM

CS

WR

RD

Peripheral

8284A

RES

clock

generator

AD

0

-AD

7

3. Status Pins

• in maximum mode only

The status pins are outputs which are used by the 8288 bus controller to generatecontrol signals according to the following table:

8088 Pin Functions

S

S

S

Meaning

0

0

0

Inter

rupt

acknowledge

(INTA)

0

0

1

I/O

read

0

1

0

I/O

write

0

1

1

HA

LT

1

0

0

Code access (fetching instruction)

1

0

1

Memory

read

1

1

0

Me

mory

write

1

1

1

Passiv

e

state

(not

used)

(

,

)

S0 S

,

and S

8088 Pin Functions

4. Bus Master pins

Control

of the loc al

bus

is transferred to

other

devices

with

the

aid

of

the

following signals: Minimum Mode - HOLD and HLDA (hold acknowledge)Maximum Mode - request/grant

a

HOLD is

an input (in minimum mode only) which tells the

processor

to

suspend

operations and allow other devices

to access

the

system

bus.

Program execution only resumes when HOLD=0.

a

HLDA (hold

acknowledge) is an output which

informs other dev ices

in the

system

that the 8088 is in a HOLD state.

When another device wants to

access the bus, it waits for HLDA=1.

(HOLD,

HLDA,

RQ/GT0,

RQ/GT1and

LOCK)

LOCK

and

)

GT

RQ

GT

RQ

docsity.com

8088 Pin Functions

5. Interrupt pins (NMI, INTR and INTA)

Interrupt acknowledge pin

is available only inminimum mode. NMI

(non-maskable interrupt) and INTR (interrupt request) are present in bothmodes.

a

The NMI (non-maskable interrupt) is an input which accepts a rising

edge

to trigger the interrupt. It cannot be disabled by software. Interrupt number2 is generated by an NMI.

a

INTR is an input which accepts a high lo

gic level as an interrupt request.

Provided the interrupt flag in the FLAGS register is enabled, the processorwill respond to the interrupt request in the same way as it processes ansoftware INT instruction.

a

_

acknowledges an interrupt request and indicates to the interrupting

device that it should place an 8-bit interrupt number on the data bus

INTA

INTA

(Refer to Part 10-Interrupt for details)

8088 Pin Functions

RESET

An

input which resets and init

ializes

the processor. After a

RESET the processor reads memory location FFFF0h for an instruction.

7. Bus control pins

A group of 7 pins that generate the control signals for data transfer to andfrom the data and address bus in minimum mode. In maximum mode onlytwo (RD and READY) of these 7 functions are available directly (the otherbus protocol signals are generated from the status pins).The seven pins in this group include:

a

READY - an input to tell the processor tha t the selected me mory or I/Oport

is

ready

to complete a read

or

write operation. If READY is

not

asserted, wait states are added (e.g. For slow memory).

8088 Pin Functions

8. Address, data pins and address status pins a

AD0-AD7 (address/data bus pins) - these pins

output

both address and data

information

and

input

data at

different

times

of

the

bus cycle. Usually an

external latch stores the address information form these pins before the pinsare switched to carry data. Both the low and high order bytes of a 16-bit dataword must be transferred via these pins.

a

A8-A15 (address

bus pins) -

used

solely

for

specifying

the

address

of a

memory location or IO port.

a

A16/S3-A19/S6 (address

bus

or

status pins) -

these

either

carry memory

addressing

information

or

status inform

ation.

S6 is always at logic 0. S

describes the state of the interrupt flag in the FLAGS register.

S4 and S

describe the segment register being used to generate the

physical address

that was output on the address during the current bus cycle.

8088 Pin Functions

a

The address pins A0-A15 specify either a 16-bit I/O port number or thefirst 16 bits of a 20-bit address of a memory location.

9. Coprocessor interaction pins

Three pins

are used for interactions b etween the

and

arithmetic

co-processor

to

synchronize

MPU

with

external hardware.

S

S

Segment

register

0

0

ES

0

1

SS

1

0

CS or no segment

1

1

DS

8. Address, data pins and address status pins (cont.)

(TEST,

QS0 and QS1)