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Main points of this exam paper are: Addition Problem, Computer Engineering, Decimal Notation, Octal Notation, Hexadecimal Notation, Six Bit Unsigned, Extra Digital, Support Subtraction, Partial Implementation, Overflow Error Detector
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4 problems, 6 pages Exam Two 13 March 2003
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 6 pages Exam Two 13 March 2003
Problem 1 (6 parts, 40 points) Numbers and Arithmetic
Part A (4 points) Convert these octal values into decimal notation:
octal notation decimal notation 73
Part B (4 points) Convert these hexadecimal values into octal notation:
hexadecimal notation octal notation 0xABC
0x3FD.E
Part C (10 points) For each problem below, (a) compute the addition using the rules of arithmetic, (b) indicate whether an error occurs assuming all numbers are expressed using a six bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a six bit unsigned representation.
result signed error? unsigned error? Part D (12 points) Convert each subtraction problem (X-Y=Z) below to an addition problem (X+(-Y)=Z) and compute the result of the addition. Also indicate whether an error occurs assuming all numbers are expressed using a six bit two’s complement representation and then indicate whether an error occurs using a six bit unsigned representation.
Result Signed Error? Unsigned Error?
4 problems, 6 pages Exam Two 13 March 2003
Problem 2 (2 parts, 20 points) Counter Design
Part A (6 points) Design a toggle cell using only transparent latches, inverters, and 2-to- multiplexers. Use icons for the latches and muxes. Your toggle cell should have an active high
toggle enable input TE , and an active low clear input Clear , two-phase non-overlapping clock
inputs Φ 1 and Φ 2 , and a single output Out. The Clear signal has precedence over TE. Label all signals.
Part B (14 points) Now use several of your toggle cells (in icon form) to build a divide by twelve counter. This design should include a count enable CE and an active high clear CLR. Your design should clear if (A) the external clear CLR is high, or (B) the maximum output count is reached and the count enable is high. Assume all toggle cells are connected to the two-phase clock. You do not need to draw in the clock signals. Use any basic gates (AND, OR, NAND, NOR, and NOT) you require. Label all signals.
4 problems, 6 pages Exam Two 13 March 2003
Problem 3 (2 parts, 15 points) Reengineering Counters
Part A (5 points) Suppose you have a counter with a count enable CE and an active high clear CLR. The counter has two outputs (O 1 and O 0 ) which form an unsigned integer (O 1 O 0 ). Its behavior is described by the following timing diagram. Each dotted vertical line denotes the end of one full clock cycle. What type of counter is this?
This is a divide by counter.
Part B (10 points) Suppose you are given the following incorrect implementation of a counter. Complete the timing diagram below by showing the outputs (O 0 and O 1 ) for clock cycles 7 through 14.
TE Out Clr
TE Out Clr
