Active Low - Computer Engineering - Exam, Exams of Computer Science

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5 problems, 7 pages Final Exam 10 June 1999

Name (print) _____________________________________________________

1 2 3 4 5 total

5 problems, 7 pages Final Exam 10 June 1999

Problem 1 (2 parts, 20 points) Two by Two

Part A (10 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output Out. The - Clear signal has precedence over TE. Label all signals.

Part B (10 points) Now combine three of these toggle cells to build a divide by seven counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected.

Problem 2 (3 parts, 28 points) Switch Design

5 problems, 7 pages Final Exam 10 June 1999

Problem 3 (3 parts, 26 points) Switch Design

Consider the following MIPS program fragment. The attached sheet lists the instruction set.

address label instruction 1000 start: addi $1, $0, 100 1004 lw $2, 0($1) 1008 addi $1, $1, 4 1012 loop: lw $4, 0($1) 1016 slt $3, $4, $ 1020 bne $3, $0, skip 1024 add $2, $0, $ 1028 skip1: addi $1, $1, 4 1032 slti $3, $1, 200 1036 bne $3, $0, loop

Part A (10 points) How many times is the loop body in this program fragment executed?

number of loop iterations:

Part B (8 points) After this fragment completes, which register (computed by this fragment) is most likely to be used elsewhere in the program that calls this fragment?

most likely shared register:

Part C (8 points) What does this program fragment accomplish?

MIPS Assembly Language

move from Hi mfhi $1 $1 = Hi

• 5 problems, 7 pages Final Exam 10 June
  • add add $1,$2,$3 $1 = $2 + $ instruction example meaning
  • subtract sub $1,$2,$3 $1 = $2 - $
  • add immediate addi $1,$2,100 $1 = $2 +
  • add unsigned addu $1,$2,$3 $1 = $2 + $
  • subtract unsigned subu $1,$2,$3 $1 = $2 - $
  • add immediate unsigned addiu $1,$2,100 $1 = $2 +
  • multiply mult $2,$3 hi, lo = $2 * $ move from coproc. register mfc0 $1,$epc $1 = $epc
  • multiply unsigned multu $2,$3 hi, lo = $2 * $
  • divide div $2,$3 lo = $2 / $3; hi $2 mod $
  • divide unsigned divu $2,$3 lo = $2 / $3; hi $2 mod $
  • and and $1,$2,$3 $1 = $2 & $ move from Lo mflo $1 $1 = Lo
  • or or $1,$2,$3 $1 = $2 | $
  • and immediate andi $1,$2,100 $1 = $2 &
  • or immediate ori $1,$2,100 $1 = $2 |
  • shift left logical sll $1,$2,5 $1 = $2 <<
  • shift right logical srl $1,$2,5 $1 = $2 >>
  • store word sw $1,100($2) memory [$2 + 100] = $ load word lw $1,100($2) $1 = memory [$2 + 100]
  • load upper immediate lui $1,100 $1 = 100 x
  • branch if equal beq $1,$2,100 if ($1 = $2), PC = PC + 4 +
  • branch if not equal bne $1,$2,100 if ($1 ≠ $2), PC = PC + 4 +
  • set if less than slt $1, $2, $3 if ($2 < $3), $1 = 1 else $1 =
  • set if less than immediate slti $1, $2, 100 if ($2 < 100), $1 = 1 else $1 =
  • set if less than unsigned sltu $1, $2, $3 if ($2 < $3), $1 = 1 else $1 =
  • set if less than imm. uns. sltiu $1, $2, 100 if ($2 < 100), $1 = 1 else $1 =
  • jump j 10000 PC =
  • jump register jr $31 PC = $
  • jump and link jal 10000 $31 = PC + 4; PC =

5 problems, 7 pages Final Exam 10 June 1999

Problem 5 (3 parts, 25 points) Short Answer

Answer the following questions concisely and legibly.

Part A (8 points) An instruction in a non-pipelined multi-cycle MIPS implementation requires fewer cycles to complete (average instruction latency) that a pipelined MIPS implementation. Why do pipelined implementations execute programs in less time?

Part B (10 points) Moore’s Law suggests that computer performance (measured in instructions per second) doubles approximately every two years. Using this heuristic, if a 1980 computer delivered one million instructions per second (MIPS), what year would we expect a one trillion operation per second machine? (trillion is a million millions.) What year (in the past) should we have had a one instruction per second machine?

year of trillion instruction per second

year of one instruction per second

Part C (7 points) What physical parameter is being forecast to replace average delay through a gate as the limiting factor in the performance of future digital computers? (This factor was discussed in class.)