High Performance Computing Lecture 4: Instruction Set Architecture and Addressing Modes, Slides of Computer Science

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High Performance Computing

Lecture 4

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Terms: Word Size, Word Alignment

The Word Size of a computer

The size of an integer or pointer on the computer 32b (4B) on many machines

Word Alignment

`Integer variable X is not word aligned’ The data item is not located at a word boundary Word boundaries: addresses 0, 4, 8, 12, … Data 1A C8 B2 46 F0 8C 1E DF Byte Address^400

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Instruction Set Architecture

 Description of machine from view of the programmer/compiler  Example: Intel ® x86 Instruction Set Architecture  Includes specification of

1. The different kinds of instructions available (instruction set)
2. How operands are specified (addressing modes)
3. What each instruction looks like (instruction format)

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Kinds of Instructions

1. Arithmetic/logical instructions  add, subtract, multiply, divide, compare (int/fp)  or, and, not, xor  shift (left/right, arithmetic/logical), rotate

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Kinds of Instructions

1. Arithmetic/logical instructions
2. Data transfer instructions
3. Control transfer instructions  jump, conditional branch, function call, return

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Kinds of Instructions

1. Arithmetic/logical instructions
2. Data transfer instructions
3. Control transfer instructions
4. Other instructions  e.g., halt

10 Addressing Modes: Operand in Register

1. Register Direct Addressing Mode Operand is in the specified general purpose register Example Suppose that the General Purpose Registers numbered as R0, R1, R2, etc ADD R1, R2, R3 / R1 = R2 + R Information that must be present in the instruction: Operation (e.g., add) Identities of source and destination registers R R R 17 24 37 61 destination operand source operands

11 Addressing Modes: Operand in Register

1. Register Direct Addressing Mode
2. Immediate Addressing Mode Operand is included in the instruction ADD R1, R2, 7 /R1 = R2 + 7 Information that must be present in the instruction: The “immediate operand” value

13 Addressing Modes: Operand in Memory

3. Register Indirect Addressing Mode
4. Base-Displacement Addressing Mode Memory address of operand is calculated as the sum of value in specified register and specified displacement ADD R1, R1, 4(R2) Information that must be present in instruction: Identity of base register (e.g., R2) Value of displacement to be added (e.g. 4) R R 32 100 Value 0 10 35 - 17 Address 96 100 104 108 MAIN MEMORY 67

14 Addressing Modes: Operand in Memory

3. Register Indirect Addressing Mode
4. Base-Displacement Addressing Mode
5. Absolute Addressing Mode Memory address of operand is specified directly in the instruction ADD R1, R2, #