Advanced Compilers - Control Flow Analysis - Lecture Slides | EECS 583, Study notes of Electrical and Electronics Engineering

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EECS 583 – Lecture 2 Control Flow Analysis

University of Michigan January 9, 2002

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Announcements^ Y^ Preliminary course webpage is available

»^ Lecture notes are there »^ Other useful info Y Reading for next week »^ “HPL-PD Architecture Specification: Version 1.

”, by Kathail,

Rau, Schlansker, http://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf » “EPIC: An Architecture For Instruction-Level ParallelProcessors”, by Schlansker and Rau http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf » “On Predicated Execution”, by Park and Schlansker” http://www.hpl.hp.com/techreports/91/HPL-91-58.pdf

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Compiler backend IR – Our input^ Y^ Variable home location »^ Frontend – every variable in memory »^ Backend – maximal but safe register promotion^ y^

All temporaries put into registers y All local scalars put into registers, except those accessed via & y All globals, local arrays/structs, unpromotable local scalars put inmemory. Accessed via load/store.

Y^ Backend IR (intermediate representation)^ »^

machine independent assembly code – really resource indep! » aka RTL (register transfer language), 3-address code » r1 = r2 + r3 or equivalently add r1, r2, r3^ y^ Opcode – not machine independent (HPL-PD, RISC++)^ y^ Operands^ X^

Virtual registers – infinite number of these X Special registers – stack pointer, pc, etc (macro regs) X Literals – compile-time constants

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Control flow^ Y^ Control transfer = branch (taken or fall-through)^ Y^ Control flow

»^ Branching behavior of an application »^ What sequences of instructions can be executed Y Execution

Æ^ Dynamic control flow

»^ Direction of a particular instance of a branch »^ Predict, speculate, squash, etc. Y Compiler

Æ^ static control flow

»^ Not executing the program »^ Input not known, so what could happen Y Control flow analysis »^ Determining properties of the program branch structure »^ Determining when instructions execution properties

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Identifying BBs - Example

L1: r7 = load(r8) L2: r1 = r2 + r3 L3: beq r1, 0, L10 L4: r4 = r5 * r6 L5: r1 = r1 + 1 L6: beq r1 100 L2 L7: beq r2 100 L10 L8: r5 = r9 + 1 L9: r7 = r7 & 3 L10: r9 = load (r3) L11: store(r9, r1)

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Control flow graph (CFG)^ Y^ Defn Control Flow Graph

Directed graph, G = (V,E)where each vertex V is abasic block and there is anedge E, v1 (BB1)

Æ^ v2 (BB2) if BB2 can immediately followBB1 in some executionsequence^ »^ A BB has an edge to allblocks it can branch to^ »^ Standard representationused by many compilers^ »^ Often have 2 pseudo V’s^ y^

entry node y exit node

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

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Dominator^ Y^ Defn: Dominator

• Given a CFG(V, E, Entry, Exit), a node x

dominates a node y, if every path from the Entry block to ycontains x Y 3 properties of dominators^ »^ Each BB dominates itself^ »^ If x dominates y, and y dominates z, then x dominates z^ »^ If x dominates z and y dominates z, then either x dominates yor y dominates x Y Intuition^ »^ Given some BB, which blocks are guaranteed to have executedprior to executing the BB^ »^ Propagate values from dominators to subsequent blocksbecause values always generated when you need them

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Dominator example

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

BB2 BB3^ BB4 BB

Entry

BB1 BB6 Exit

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Immediate dominator^ Y^ Defn: Immediate dominator^ (idom)– Each node n has aunique immediate dominatorm that is the last dominatorof n on any path from theinitial node to n »^ Closest node that dominates

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

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Post dominator^ Y^ Defn: Post Dominator

• Given a CFG(V, E, Entry, Exit), a

node x post dominates a node y, if every path from y to theExit contains x Y Intuition^ »^ Given some BB, which blocks are guaranteed to have executedafter executing the BB^ »^ Propagate values from blocks to post dominators, make aguess about something in a BB, check if you were right in thepost dominator

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Post dominator analysis^ Y^ Compute pdom(BBi) = set ofBBs that post dominate BBi^ Y^ Initialization »^ Pdom(exit) = exit »^ Pdom(everything else) = allnodesIterative computation Y »^ while change, do^ y^

change = false y for each BB (except the exitBB)^ X^ tmp(BB) = BB +{intersect of pdom ofall successor BB’s}^ X^ if (tmp(BB) != pdom(BB))^ ± pdom(BB) = tmp(BB) ± change = true

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

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Immediate post dominator^ Y^ Defn: Immediate post^ dominator

(ipdom) – Each node n has a uniqueimmediate post dominator mthat is the first postdominator of n on any pathfrom n to the Exit^ »^ Closest node that postdominates^ »^ First breadth-firstsuccessor that postdominates a node

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

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Backedge example

BB2 BB3^ BB4 BB

Entry

BB1 BB6 Exit

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Loop detection^ Y^ Identify all backedges using Dom info^ Y^ Each backedge (x

Æ^ y) defines a loop

»^ Loop header is the backedge target (y) »^ Loop BB – basic blocks that comprise the loop^ y^

All predecessor blocks of x for which control can reach x withoutgoing through y are in the loop

Y^ Merge loops with the same header^ »^

I.e., a loop with 2 continues » LoopBackedge = LoopBackedge1 + LoopBackedge2 » LoopBB = LoopBB1 + LoopBB

Y^ Important property^ »^

Header dominates all LoopBB