Introductory Course, Syllabus for Advanced Compilers | EECS 583, Study notes of Electrical and Electronics Engineering

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EECS 583 – AdvancedCompilers

Winter 2002, University of Michigan Scott Mahlke (mall-key) Lecture 1 January 7, 2002

Class Overview Y

This class is NOT about:

Programming languages (despite what the time table says) » Parsing, syntax checking » Handling advanced language features – virtual functions, inheritance » Frontend transformations – array dependence analysis, loop xforms » Debugging » Simulation Y

Compiler backend

Mapping applications to processor hardware » Retargetability – work for multiple platforms (not hard coded) » Work at the assembly-code level y Processor independent -> Machine code » Speed/Efficiency y How to make the application run fast y Use less memory (text, data)

Textbook and other classroom material Y

No required text

Lecture notes » Papers/reports Y

Recommended reference texts

“Compilers: Principles, Techniques, Tools”, by Aho, Sethi, Ullman (akared dragon book) » “Building an Optimizing Compiler”, by Morgan Y

Other useful material

Trimaran webpage: http://www.trimaran.org » UIUC Impact webpage: http://www.crhc.uiuc.edu/Impact Y

Course webpage + course newsgroup

Will be set up later this week » Lecture notes ++ » Newsgroup – forum for helping each other, I will try to checkregularly

What the Class Will be Like Y

Class meeting time – 3:30 – 6:00, MW

2.5 hrs is WAY too much » 1.5 hrs is a good estimate (ie 3:30 – 5:00) » But, may be longer if we have a lot of material to get through Y

First half: 400-level class

Text book material – basic of compiler backend techniques » I lecture, you guys do homeworks » Midterm exam Y

Second half: 500-level class

Research papers » Discussion » Presentations by students – You guys are going to teach

Course Grading Y

Yes, everyone will get a grade

Distribution of grades, scale, etc - ??? » Most (hopefully all) will get A’s and B’s » Slackers will be obvious and will suffer » If you wanted a blow off class – consider dropping Y

Components

Midterm exam – 30% y No final y In class, 2 hr exam, exact date TBD » Project – 40% » Homeworks – 15% » Class participation – 15%

Homeworks Y

3-5 of these

Small/modest programming assignments » Problems to work out by hand » 1 homework every 2 weeks Y

Goals

Learn the important concepts » Practice for the midterm » Learn the compiler infrastructure so you can do the project Y

Grading will be lax

Pass/Fail » Students will be asked to present their solns to the class Y

Working together is ok

Make sure you understand things or it will come back to bite you

Class Participation Y

Interaction and discussion is essential in a graduate class

Participation is a big part of your grade y Subjective on my part » Be here » Don’t just stare at the wall » Be prepared to discuss the material » Have something useful to contribute Y

Opportunities for participation

Research paper discussions – thoughts, comments, etc » Saying what you think in the special interest group meetings » Solving the problem of the day » Presenting homework solns » Feedback to me about the class Y

More opportunities for participation will be possible as we go along

Special Interest Groups Y

Divide up the class into 4 focus groups

Each group will meet every other week for 1 hr (time/place TBD) » Identify research papers, discuss papers » Define class projects, break down the work » Present material to rest of class Y

4 groups – equal number of people in each group

Memory hierarchy optimization » Scheduling, register allocation » Dataflow analysis, optimization » Control flow analysis, region formation Y

FAQ

Do I have to be in a group – Yes » Can I be in more than 1 group – No » Do I get to pick which group I am in – Sort of » What if I get put in a group that I do not want to be in - Tough

Topic outline – 1 to 2 lectures per topic Y

First half of the class

Today: VLIW architectures » Control flow analysis » Trimaran compiler system » Dataflow analysis » Region formation, If-conversion » Local optimizations » Global/loop optimizations » Machine description » Scalar scheduling » Modulo scheduling » Register allocation » Cache prefetching

My goals – Awaken some interest in CompilersHere Y

Traditional strength at Michigan - Architecture

Superscalar processors, do everything in hardware » Emphasis on Pentium class architectures Y

Little on compilers

Hardware people have to understand compilers y No attention to compilers -> bad processor design » 483 material is not what real compiler people focus on y Parsing, syntax checking, etc – Standard, mature field » This class material is where all the action is at y How to make code run fast (approach hand coding) y How to reduce power y How to reduce code size y How to make use of unusual architectural features y How to design better processors y How to design customized processors

• 15 - Defining Attributes of VLIW/EPIC Y

1. MultiOp: instruction containing multiple independent operations

Y

2. Specified number of resources of specified types

Y

3. Exposed, architectural latencies

Add

Add

Mpy

Mem

Mem

Register File

add

nop

nop

load

store

VLIW instruction = 5 independent operations

Icache

UAL vs NUAL Y

A conventional sequential program has unit assumed latency (UAL)

Semantics of the program are understood by assuming eachinstruction is completed before the next one is issued Y

A program has non-unit assumed latency (NUAL) if:

At least 1 operation has a non-unit assumed latency, L, which isgreater than 1 » The semantics of the program are correctly understood if exactly thenext L-1 instructions are understood to have issued before thisoperation completes

VLIW/EPIC Advantages and Disadvantages Y

Advantages

No run-time dependence checks against previously or simultaneouslyissued operations » No run-time scheduling decisions » No register renaming » Rely on the compiler to do all the work » SIMPLER hardware, more effective (larger scope!) Y

Disadvantages

No tolerance for different or variable latencies » No tolerance for a difference in the set of function units » No object code compatibility » More complex compiler

Compiler’s role in a VLIW/EPIC processor Y

Record of Execution

What time each operation executes » What resource(s) each operation uses Y

Compiler needs to

Create ROE Y

Processor

Needs a mechanism to create a ROE » Communicate ROE from software to hardware Y

Efficient ROE’s difficult to achieve so features added toVLIW/EPIC processors to make the job easier

Predicated exection » Control speculation » Data speculation » Cache placement opcodes » Rotating registers