advanced computer architecture
basic block - correct answera sequence of instruction with exactly one entrance and one
exit. If execution reaches the first instruction in a basic block then it is guaranteed that
all of the instructions within basic block will be executed
branch bias - correct answera conditional branch instruction that almost always exhibits
the same taken/not-taken status each time it executes
cache pollution - correct answerwhen a useless prefetch block replaces a useful cache
block (demand or prefetches correctly)
content addressable memory - correct answera generic digital logic memory a full-
associative RAM. All entries are searched in parallel for the input value. Must be kept
small capacity. Used in several different places in modern architectures
Demand access - correct answera memory access caused by actual program
instructions. Could be an actual instruction fetch. Or an access using an effective
address calculated by load and/or store instructions
dynamic branch prediction - correct answereach a CTI is fetched, predict the outcome
(taken vs. not-taken) based on past history
fetch bundle - correct answergroup of instructions fetched at the same time
lane - correct answerthe path an instruction could possible take through a superscalar
processor. For a 2-wide superscalar there are two lanes. For 3-wide superscalar, there
are three lanes
linked data structures - correct answerthe generic term for any software data structure
that retains not only data value(s). But also reference(s) to other items of data that are
logically adjacent. The reference is an address, which is the link to the other items.
miss cache - correct answercopies information into miss cache when ever it misses
pointer chasing - correct answerin order to access the 2nd node you must first access
the 1st node in order to access the 3rd node you must first access the 2nd node and on
and on
prefetch - correct answercheck the memory hierarchy for cache block data before the
program actually needs the data. Bring block data into higher level cache early. Used
not just for instruction fetches. But any memory access
