Assignment 2
Due Date: Monday 20th July 2020, before 1800hrs
Submission procedure:
1. Assignments can be submitted as typed word document OR in handwritten form. For handwritten
assignments, use software app (like Microsoft office lens or CamScanner etc.) to straighten your
images and convert those to a single pdf document. Make sure that text is readable.
2. Email your assignments to: [email protected]
3. Subject line of your mail should have only following text “CS504 – A2”
4. File name should be as follows;
ACA - A x - Name – Regid e.g. “ACA - A 2 – Muhammad Ali – 1234”.
Q1: [5]
Imagine you have been offered an internship at a processor design company. Understanding that your
strength is hardware design, they have given you a task to recommend what would be the better trade-
off between the following two options of pipelining a currently unpipelined processor:
a) Six stage pipe-line with Clock rate 4.5 times faster than unpipelined clock, but 9% of the instructions
need to stall for one cycle.
b) Seven stage pipeline with Clock rate 5 times fast, but 5% of instructions need to stall for one cycle
and 10% of instructions need to stall for 3 cycles.
What option would you recommend? Clearly elaborate your calculations; you will not be graded on the
right choice but on your calculations.
Q2: [5+5]
The figure below shows pipelined RISC V architecture without stall or forwarding logic. We want to add
only one bypass path from MEMORY ACCESS stage to 2nd operand (Register B in diagram) at the end of
Decode stage.
a) Design complete logic including control signals for the mentioned bypass path.
b) Design logic for stalling processor in all other case
