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EE 231
Homework Assignment 5
Due Oct. 1, 2008
1.Problem 4.
2.Problem 4.6. For Part (b), you do not have to simulate the design.
3.Problem 4.
4.Problem 4.
5.Problem 4.
6.Problem 4.
7.Problem 4.
8.Problem 4.
9.Problem 4.52. You do not need to simulate the design.
For the circuit shown in Figure 4.13 of the text, verify that the V output bit is correct for the addition
operation. That is, show that (a) V will be 1 when you add two positive numbers together (B3 = 0 and
A3 = 0) and get a negative number (S3 = 1), (b) V will be 1 when you add two negative numbers
together (B3 = 1 and A3 = 1) and you get a positive number (S3 = 0), and (c) the V output will be 0 in
all other circumstances (adding two positives and getting a positive, adding two negatives and getting a
negative, or adding a positive and a negative number).
EE 231 Homework Assignment #5 http://www.ee.nmt.edu/~rison/ee231/hw/hw05.html
1 of 1 10/1/2008 7:24 PM
hw05_soln Page 1
// Problem 4. // // Verilog dataflow program for fourโbit full adder/subtractor module four_bit_add_sub ( input [3:0] A, B, input M, output [3:0] S, output C, V);
// Make C and S into a 5โbit number // If M is 1 (true), subtract B from A; the 5th bit is borrow // If M is 0 (false), add B to A; the 5th bit is carry assign {C, S} = M? A โ B : A + B;
// If M is 1 (subtract), V is set when Pos โ Neg = Neg or Neg โ Pos = Pos // If M is 0 (add), V is set when Pos + Pos = Neg or Neg + Neg = Pos assign V = M? (~A[3] & B[3] & S[3]) | ( A[3] & ~B[3] & ~S[3]) : ( A[3] & B[3] & ~S[3]) | (~A[3] & ~B[3] & S[3]) ;
endmodule
// โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ // Problem 4.52 (a) // // Verilog dataflow program to increment a four bit number module four_bit_inc (input [3:0] A, output [3:0] S); assign S = A + 1; endmodule
// Problem 4.52 (b) // // Verilog dataflow program to decrement a four bit number module four_bit_dec (input [3:0] A, output [3:0] D); assign D = A โ 1; endmodule
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ Problem 11.
We are looking at the V output for addition (M = 0), so the B signals going into the full adders are not inverted.
There are six possible things to consider:
(a) Show V = 0 after Pos + Pos = Pos A3 is 0, B3 is 0, S3 is 0 (b) Show V = 1 after Pos + Pos = Neg A3 is 0, B3 is 0, S3 is 1 (c) Show V = 0 after Neg + Neg = Neg A3 is 1, B3 is 1, S3 is 1 (d) Show V = 1 after Neg + Neg = Pos A3 is 1, B3 is 1, S3 is 0 (e) Show V = 0 after Pos + Neg = Pos A3 is 0, B3 is 1, S3 is 0 (f) Show V = 0 after Pos + Neg = Neg A3 is 0, B3 is 1, S3 is 1
(a) Consider the full adder on the left side of figure 4.13. The A3 and B inputs are 0. Since the result is positive, S3 is 0. For this to happen, C has to be 0. C4 will be 0 (0 + 0 + 0 does not generate a carry). In this case, V = C3 xor C4 = 0 xor 0 = 0. Pos + Pos = Pos produces V = 0.
(b) The A3 and B3 inputs are 0. Since the result is negative, S3 is 1. For this to happen, C3 has to be 1. C4 will be 0 (0 + 0 + 1 does not generate a carry). In this case, V = C3 xor C4 = 1 xor 0 = 1. Pos + Pos = Neg produces V = 1.
(c) The A3 and B3 inputs are 1. Since the result is negative, S3 is 1. For this to happen, C3 has to be 1 (input 1 + 1 + 1 produces S = 1, whereas input 1 + 1 + 0 would produce S = 0). C4 will be 1 (1 + 1 + 1 generates a carry). In this case, V = C3 xor C4 = 1 xor 1 = 0. Neg + Neg = Neg produces V = 0.
(d) The A3 and B3 inputs are 1. Since the result is positive, S3 is 0. For this to happen, C3 has to be 0 (input 1 + 1 + 1 would produce S = 1, whereas input 1 + 1 + 0 produces S = 0). C4 will be 1 (1 + 1 + 0 generates a carry). In this case, V = C3 xor C4 = 0 xor 1 = 0. Neg + Neg = Pos produces V = 1.
(e) A3 is 1 and B3 is 0. (Same if A3 is 0 and B3 is 1.) Since the result is
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postive, S3 is 0. For this to happen, C3 has to be 1 (input 1 + 0 + 1 produces S = 0, whereas input 1 + 0 + 0 would produce S = 0). C4 will be 1 (
- 0 + 1 generates a carry). In this case, V = C3 xor C4 = 1 xor 1 = 0. Pos + Neg = Pos produces V = 0.
(f) A3 is 1 and B3 is 0. (Same if A3 is 0 and B3 is 1.) Since the result is negative, S3 is 1. For this to happen, C3 has to be 0 (input 1 + 0 + 0 produces S = 1, whereas input 1 + 0 + 1 would produce S = 0). C4 will be 0 (1 + 0 + 0 does not generates a carry). In this case, V = C3 xor C4 = 0 xor 0 = 0. Pos + Neg = Neg produces V = 0.
