Computer Architecture & Organization: A Top-Level View of Function and Interconnection, Lecture notes of Computer Architecture and Organization

A Top-Level View of Computer Function and Interconnection

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2019/2020

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EEC 216
Computer Architecture and
Organization
Spring 2020
Lecture #2
Dr. Mohamed Issa
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EEC 216

Computer Architecture and

Organization

Spring 2020

Lecture

Dr. Mohamed Issa

Chapter 3. A Top-Level View

of Computer Function and

Interconnection

Program Concept

  • Using a fixed set of logic components, there are

two ways to build a system that performs a specific

computation on some input data:

1. Special-purpose (customized) hardware:

  • Logic components are connected and configured specifically to perform a particular computation.
  • Type of computation is specified by way in which components are connected/configured  hardwired programming.
  • To change computation, rewire components  inflexible!

2. General-purpose hardware:

  • Logic components are connected to form a general-purpose hardware that gets configured using set of input control signals.
  • Type of computation (reflected by control signals values) is specified by sequence of input codes  software programming.
  • To change computation, change code  flexible!

Sequence of

arithmetic and logic

functions

Data Results

Customized hardware

General-purpose

arithmetic and logic

functions

Data Results

Instruction

Interpreter

Instruction codes

Control signals

  • Each code is an instruction.
  • A sequence of codes (or instructions) is called CPU^ software.

Computer Components

  • Each computer component takes some part in

implementing the “s/w programming” approach:

—Control unit (CU) acts as instruction interpreter.

—Arithmetic and logic unit (ALU) implements general-

purpose arithmetic and logic functions.

—Both CU and ALU constitute most of central processing

unit (CPU).

—Data/codes get into system, and results get out

through input/output (I/O) units.

—Data, code, and results are stored temporarily while

being processed in main memory (MM) unit.

Fetch Cycle

  • Program Counter (PC) holds address of next

instruction to fetch.

  • Processor fetches instruction from memory

location pointed to by PC.

  • Increment PC.

— Unless told otherwise

  • Instruction loaded into Instruction Register (IR).
  • Processor interprets instruction and performs

required actions in execute cycle.

Execute Cycle

  • Processor-memory

— Data transfer between CPU and main memory

  • Processor-I/O

— Data transfer between CPU and I/O module

  • Data processing

—Some arithmetic or logical operation on data

  • Control

— Alteration of sequence of operations

— e.g., jump

  • Combination of the above

First instruction

Second instruction

Third instruction

Fetch cycle Execute cycle

Instruction Cycle: State Diagram

CPU-memory or CPU-I/O operations

Internal CPU operations

Transfer of Control via Interrupts

Program Flow Control

Interrupt Cycle

  • Added to instruction cycle.
  • Processor checks for interrupt

—Indicated by an interrupt signal

  • If no interrupt:

—fetch next instruction

  • If interrupt pending:

—Suspend execution of current program.

—Save context (PC & relevant data).

—Set PC to start address of interrupt handler routine.

—Process interrupt.

—Restore context and continue interrupted program.

Instruction Cycle (with interrupts)