Computer Function and Interconnection - Intro to Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

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A Top-Level View of Computer

Function and Interconnection

Computer Components

• Today we’ll go over: Von Neumann Architecture, Hardware and Software Approaches, Computer Functions, Interrupts, and Buses.

Hardware and Software Approaches

More Components..

• I/O Components: a module that accepts data, and instructions and converts them into instruction signals usable by the system. It can also report results in the form of an output module.
• Memory: A place to store instructions and data temporarily. (Von Neumann pointed out that the same memory could be used to store both instructions and data).

Computer Function

• The basic function of a computer is to execute a program.
• In its simplest form, instruction processing consists of two steps: The processor reads (fetches) instructions from memory one at a time and executes each instruction.
• Processing required for a single instruction is called an instruction cycle.
• The instruction cycle has two steps: the fetch cycle and the execute cycle.

Instruction Fetch and Execute

The instruction is then loaded into a register known as the Instruction Register (IR).

Instruction Execution

Interrupts

 A mechanism by which other modules may interrupt the normal processing of the processor.

Classes of Interrupts  Program: Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, or reference outside a user’s allowed memory space..

Interrupts.. Why bother?

 They are provided as a way to improve processing efficiency!  For example.. Most external devices are much slower than the processor. Suppose the processor is transferring data to a printer using the instruction cycle. After each write operation, the processor must pause and remain idle until the printer catches up. The length of this pause may be on the order of hundred or even thousands of instruction cycles that do not involve memory. What a waste!

Instruction cycle with Interrupts

Bus Interconnection

 A bus is a communication pathway connecting two or more devices. It is a shared transmission medium. However, only one device can transmit successfully at a time.  A bus typically consists of multiple communication pathways, or lines. Each line is capable of transmitting signals representing binary 1 and binary 0. Eventually, a sequence of binary digits can be transmitted across a single line. Taken together, several lines of a bus can be used to transmit binary digits simultaneously. (EX: 8-bit unit of data can be transmitted over 8 bus lines.)

Bus Structure

• A system bus consists from about 50 to hundreds of separate lines. Each line is assigned a particular meaning or function.
• Although there are many different bus designs they can all be classified into three functional groups: data, address, and control lines.

Bus Structures (cont.)

Typical Control Lines:  Memory write: causes data on the bus to be written into the addressed location.  Memory read: causes data from the addressed location to be placed on the bus.  I/O write: causes data on the bus to be output to the addressed I/O port.  I/O read: causes data from the addressed I/O port to be placed on the bus.  Transfer ACK: indicates that data have been accepted from or placed on the bus.  Bus Request: indicates that a module needs to gain control of the bus.  Bus Grant: bus. indicates that the requesting module has been granted control of the  Interrupt Request: Indicates that an interrupt is pending.  Interrupt ACK: Acknowledges that the pending interrupt has been recognized.  Clock: Is used to synchronize operations  Reset: Initializes all modules

Multiple-Bus Hierarchies

If a great number of devices are connected to the bus, performance will suffer because:  In general, the more devices attached to the bus, the greater the bus length and greater delay.  Bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus.

So.. Because of this, it is important to have a hierarchy.