Basic Control Flow Analysis - Lecture Slides - Fall 2003 | EECS 583, Study notes of Electrical and Electronics Engineering

Material Type: Notes; Professor: Mahlke; Class: Advanced Compilers; Subject: Electrical Engineering And Computer Science; University: University of Michigan - Ann Arbor; Term: Winter 2003;

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EECS 583 – Lecture 2
Basic Control Flow Analysis
University of Michigan
January 8, 2003
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EECS 583 – Lecture 2 Basic Control Flow Analysis

University of Michigan January 8, 2003

  • 1 -

Compiler Backend IR – Our input^ Y^ Variable home location

»^ Frontend – every variable in memory »^ Backend – maximal but safe register promotion^ y^

All temporaries put into registers y All local scalars put into registers, except those accessed via & y All globals, local arrays/structs, unpromotable local scalars put inmemory. Accessed via load/store.

Y^ Backend IR (intermediate representation)^ »^

machine independent assembly code – really resource indep! » aka RTL (register transfer language), 3-address code » r1 = r2 + r3 or equivalently add r1, r2, r3^ y^ Opcode – not machine independent (HPL-PD, RISC++)^ y^ Operands^ X^

Virtual registers – infinite number of these X Special registers – stack pointer, pc, etc (macro regs) X Literals – compile-time constants

  • 3 -

Basic Block (BB)^ Y^ Group operations into units with equivalent executionconditions^ Y^ Defn: Basic block

  • a sequence of consecutive operations

in which flow of control enters at the beginning andleaves at the end without halt or possibility of branchingexcept at the end^ »^ Straight-line sequence of instructions^ »^ If one operation is executed in a BB, they all are Y Finding BB’s^ »^ The first operation starts a BB^ »^ Any operation that is the target of a branch starts a BB^ »^ Any operation that immediately follows a branch starts a BB

  • 4 -

Identifying BBs - Example

L1: r7 = load(r8) L2: r1 = r2 + r3 L3: beq r1, 0, L10 L4: r4 = r5 * r6 L5: r1 = r1 + 1 L6: beq r1 100 L2 L7: beq r2 100 L10 L8: r5 = r9 + 1 L9: r7 = r7 & 3 L10: r9 = load (r3) L11: store(r9, r1)

  • 6 -

Weighted CFG^ Y^ Profiling

  • Run the application

on 1 or more sample inputs,record some behavior^ »^ Control flow profiling**^ y^

edge profile y block profile

»^ Path profiling »^ Cache profiling »^ Memory dependenceprofiling Y Annotate control flow profileonto a CFG

Æ^ weighted CFG

Y^ Optimize more effectively withprofile info!!^ »^

Optimize for the commoncase » Make educated guess

Entry^20 BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit 10

  • 7 -

Dominator^ Y^ Defn: Dominator

  • Given a CFG(V, E, Entry, Exit), a

node x dominates a node y, if every path from the Entryblock to y contains x Y 3 properties of dominators^ »^ Each BB dominates itself^ »^ If x dominates y, and y dominates z, then x dominates z^ »^ If x dominates z and y dominates z, then either x dominates y ory dominates x Y Intuition^ »^ Given some BB, which blocks are guaranteed to have executedprior to executing the BB

  • 9 -

Dominator Analysis^ Y^ Compute dom(BBi) = set ofBBs that dominate BBi^ Y^ Initialization

»^ Dom(entry) = entry »^ Dom(everything else) = allnodes Y Iterative computation »^ while change, do^ y^

change = false y for each BB (except theentry BB)^ X^ tmp(BB) = BB + {intersectof Dom of all predecessorBB’s}^ X^ if (tmp(BB) != dom(BB))^ ± dom(BB) = tmp(BB) ± change = true

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

  • 10 -

Immediate Dominator^ Y^ Defn: Immediate dominator^ (idom)– Each node n has aunique immediate dominator mthat is the last dominator of non any path from the initialnode to n »^ Closest node that dominates

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

  • 12 -

Post Dominator^ Y^ Reverse of dominator^ Y^ Defn: Post Dominator

  • Given a CFG(V, E, Entry, Exit),

a node x post dominates a node y, if every path from y tothe Exit contains x Y Intuition^ »^ Given some BB, which blocks are guaranteed to have executedafter executing the BB

  • 13 -

Post Dominator Examples

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

BB2 BB3^ BB4 BB

Entry

BB1 BB6 Exit

  • 15 -

Immediate Post Dominator^ Y^ Defn: Immediate post^ dominator

(ipdom) – Each

node n has a unique immediatepost dominator m that is thefirst post dominator of n onany path from n to the Exit^ »^ Closest node that postdominates^ »^ First breadth-first successorthat post dominates a node

Entry^ BB1 BB2^ BB3^ BB4 BB5 BB6^ BB7^ Exit

  • 16 -

Class Problem 2

Entry^ BB

Calculate the PDOM set for each BB

BB^

BB

BB^

BB

BB6 BB7 Exit

  • 18 -

Natural Loops^ Y^ Cycle suitable for optimization

»^ Discuss opti later Y 2 properties »^ Single entry point called the header^ y^

Header dominates

all blocks in the loop

»^ Must be one way to iterate the loop (ie at least 1 path back to theheader from within the loop) called a backedge Y Backedge detection »^ Edge, x

Æ^ y where the target (y) dominates the source (x)

  • 19 -

Backedge Example

BB2 BB3^ BB4 BB

Entry

BB1 BB6 Exit