Behavioral Hardware Description - Functional Verification - Lecture Slides, Slides of Computer Science

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Behavioral Hardware Description

Languages

Behavioral Hardware Description

Languages

• Behavioral vs.. RTL Thinking
• Gotta have style
• Structure of Behavioral Code
• Data Abstraction
• HDL Parallel Engine
• Verilog Portability Issues

Behavioral vs.. RTL Thinking

(continued)

• Subset of VHDL or Verilog for RTL coding has been developed based on synthesis tools.
• Structured for hardware structures and logical transformations (to match synthesis technology.
• This becomes insufficient when writing testbenches.
• If this mindset is kept – verification task becomes tedious and complicated.

Behavioral vs.. RTL Example

REQ=1 ACK==1 REQ=

ACK==0 ACK==

ACK==

Behavioral vs.. RTL Example

(continued)

• RTL Thinking (Continued)

SEQ: process (CLK) Begin If CLK’event and CLK = ‘1’ then If RESET = ‘1’ then STATE <= ….; Else STATE <= NEXT_STATE; End if; End if; End process SEQ;

Behavioral vs.. RTL Example

(continued)

• Behavioral Thinking

Process Begin … Req <= ‘1’; Wait until ACK = ‘1’; REQ <= ‘0’; Wait until ACK = ‘0’; … End process

Structure of Behavioral Code

• Structure for maintainability
  • Encapsulation hides implementation details
  • Structuring is the process of allocating portions of the functionality to different modules or entities.
  • Structure behavior based on functionality or need.

VHDL vs.. Verilog Structures

VHDL Verilog

Entity and Architecture Module

Procedure Task

Function Function

Package and Package

Body

Module

Data Abstraction

• Need ability to make testbench easier to understand
• Use Data Abstraction
  • Reals
  • Records
  • Multi-dimensional arrays
  • Lists
  • Files
  • Interfacing High-Level Data Types

Data Abstraction - Reals

• Synthesizeable models limited
  • Bits, bit vectors, integers
• Behavioral only has language limitations
• Work at same level as design
  • ATM Cell
  • SONET Frame
  • PCI Action

Data Abstraction in Verilog : ‘Real’

• Could use “’define” symbols for floating point ‘define a0 0. ‘define a1 1.
• Violates data encapsulation principle
• Defines are global, thus polluting name space
  • Using parameters is better approach Parameter a0 = 0.5000000, a1 = 1.125987;

Data Abstraction in Verilog : ‘Real’

(continued)

• Implement the filter using a function
  • Verilog has a limitation:
    • real numbers:
      • Can not be passed across interfaces in a function
      • Can not be passed in tasks
      • Module ports can not accept them
    • Use built-in feature $realtobits and $bitstoreal to translate across the interface

Data Abstraction in VHDL : ‘Real’

• Use a constant array of reals Type real_array_typ is array(natural range<>) of real; Constant a: real_array_typ(0 to 2) := (0.5, 1.125987); …
• Can use for-loop to compute equation
• Simple
• Efficient
• Independent of number of terms in the filter
• Function variable are dynamic
• Created every time procedure is called thus cannot maintain state of filter as a variable local to function
• Can not use globals – VHDL function can not have side effects, procedures can

Data Abstraction: ‘Records’

• Ideal for representing packets or frames

where control or signaling information is

grouped with user information

• Example: ATM cell
  • 53 byte packet
  • 48 bytes are payload
• VHDL nor Verilog support Variant records