Behavioral Modeling with Procedures: Controlling Operations using P, K, and R, Slides of Verilog and VHDL

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Project Step 5

Step 2 in behavioral modeling. Use

of procedures.

The nature of the process

• Will still use P, K, and R to control the

operation.

• Previously have use Pctl to compute Pint, Kctl

to compute Ki, and then Rctl to generate the

final result.

• Now will use a combined P&K&R to choose

the operation being performed

• For op A have P,K,R of 1100,1111,
• For op A AND B have 1000,1111,
• For op A + B have 0110,0001,

Note on operations

• For logical operation can do vector operations
  • Zout <= A AND B;
  • Where A and B are the input bit vectors
  • And the vectors must be of the same size for a bit-wise vector operation
• Arithmetic operations will need procedures
  • One for Add
  • One for 2’s complement
  • One for Subtract that can be an implementation of binary subtraction, or subtraction using 2’s complement addition

The procedures

• The procedures are to be declared in the

declarative region of the process

• In the declarative region of the process can

only declare a procedure body. And thus no

procedure declaration part is done.

• Scope of procedure is limited to just this

process. (We will later move these to a

package and write the procedure declaration.)

Unconstrained declaration

• PROCEDURE binadd (l,r : IN BIT_VECTOR;
• cin : IN BIT;
• sum : OUT BIT_VECTOR;
• cout : OUT BIT) IS
• VARIABLE carry : BIT: --internal variable carry
• BEGIN
• carry := cin;
• FOR i IN l’reverse_range LOOP
• -- compute sum for position I, sum := …
• -- compute carry out for position I into carry variable, carry := …
• END LOOP;
• -- assign cout from final value of carry
• • • I provide a lot but you must finish this

Highlights on the code

• Inputs are “unconstrained” – they can be any size
• We will later use these same procedures in a package

and the data size will be 16 bits.

• Outputs of the procedure are variables. These need

to be assigned to the appropriate signal.

• Need to use attribute for loop parameter as shown
  • If L declared (x downto 0) such that leftmost bit is the msb and highest index
  • THEN L’REVERSE_RANGE has the designation 0 to x

Overall look of code – where things go

• Same ENTITY as before
  • ARCHITECTURE v_3 OF adder_8 IS
  • BEGIN
    • --A single process as just described
    • PROCESS (sensitivity list)
      • **** PROCEDURES are declared here ****
      • Local Variables
    • BEGIN
      • opersw:=
      • CASE opersw…….
    • END PROCESS;
  • END v_3;