Behavioral Description - HDL Design - Assignment, Exercises of Verilog and VHDL

Project Assignment #7

2) The task is to write a behavioral description of a set of 16 16-bit dual-ported registers for the

datapath that we discussed. Behavioral means that you will use a process statement. The signals

used to interface to the two busses are the register number to be accessed, a load signal which

tells the register when to latch the data, and a drive signal that tells the register when to place the

data on the bus. Note that the register set knows nothing about time, only the value of the control

signals. Also remember that the registers are dual ported and can be loaded from and/or drive the

busses simultaneously, i.e., for example you can be loading register 0 from the ABUS and at the

• Loading a value into the register: Bus must be driven by another device which places data on

the bus at 10 ns and keeps data on the bus until 80 ns. The value on the bus is latched into the

named register on the rising edge of that bus’s load signal at 70ns. The processor’s controller

would insure the timing of the load signal. At this point the timing of the load signal is

controlled by the test bench.

• Driving a value on the bus: When the drive signal goes low, place contents of named register

on the bus and continue driving the value on the bus until the drive signal goes high.

BBUS

AregNo

Aload

Adrive

BregNo

Bload

Bdrive